Exploració per tema "Table lookup"

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    • FPGA implementation of memory-based digital predistorters with high-level synthesis 

      Li, Wantao; Guillena Berenguer, Estefanía; Montoro López, Gabriel; Gilabert Pinal, Pere Lluís (Institute of Electrical and Electronics Engineers (IEEE), 2021)
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      This paper presents a scalable look-up table (LUT) architecture for implementing digital predistortion (DPD) linearizers in a field programmable gate array (FPGA) by using the high-level synthesis (HLS) software. This ...