Exploració per tema "FPGA"
Ara es mostren els items 153-172 de 200
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LEGION-based image segmentation by means of spiking neural networks using normalized synaptic weights implemented on a compact scalable neuromorphic architecture
(2019-01-01)
Article
Accés obertLEGION (Locally Excitatory, Globally Inhibitory Oscillator Network) topology has demonstrated good capabilities in scene segmentation applications. However, the implementation of LEGION algorithm requires machines with ... -
Link Layer Optimization of an FPGA-based Transceiver for Free-Space Optical Communication
(Universitat Politècnica de Catalunya, 2015-07)
Projecte Final de Màster Oficial
Accés restringit per decisió de l'autorIn the relentless pursuit to meet the ever-increasing need for higher communication bandwidths, free-space optical communications shows up as a suitable alternative for particular application areas. Due to the nature of ... -
Monitorització de bus can amb compact-rio
(Universitat Politècnica de Catalunya, 2007-02)
Projecte/Treball Final de Carrera
Accés restringit per acord de confidencialitat -
Módulo de una papelera de reciclaje automatizada para cocina
(Universitat Politècnica de Catalunya, 2019-10-31)
Treball Final de Grau
Accés restringit per decisió de l'autor[CASTELLÀ] Este proyecto persigue automatizar y facilitar la vida a las personas y sus actividades diarias. El objetivo es modelizar la recogida de basura en cada hogar para su mejor evacuación, y si es necesario, también ... -
Multi-camera PCIe Frame Grabber for ADAS and autonomous driving applications
(Universitat Politècnica de Catalunya, 2020-06)
Treball Final de Grau
Accés restringit per acord de confidencialitat -
New Architecture for an Image Compression Algorithm for Embedded Systems
(Universitat Politècnica de Catalunya, 2023-10-18)
Projecte Final de Màster Oficial
Accés restringit per acord de confidencialitatNew, cheaper, and more efficient SoC architectures appear year over year in the market. With this SoCs, HP Inc. develops new products trying to achieve cheaper costs and improve performance compared to previous products ... -
New Hardware Architecture for Low-Cost Functional Test Systems Applications to HDMI generation
(Universitat Politècnica de Catalunya, 2011-07-26)
Projecte/Treball Final de Carrera
Accés obertEnglish: Development of a new test hardware architecture for functional test systems. Development of a proof-of-concept prototype for HDMI generation. -
Object Recognition using FPGA
(Universitat Politècnica de Catalunya, 2011-11-22)
Projecte Final de Màster Oficial
Accés obertEnglish: Computer vision is the field concerned with the automated processing of images from the real world to extract and interpret information on a real time basis. There are a wide range of tasks such as controlling the ... -
OmpSs@cloudFPGA: An FPGA task-based programming model with message passing
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertNowadays, a new parallel paradigm for energy-efficient heterogeneous hardware infrastructures is required to achieve better performance at a reasonable cost on high-performance computing applications. Under this new paradigm, ... -
OmpSs@FPGA framework for high performance FPGA computing
(Institute of Electrical and Electronics Engineers (IEEE), 2021-12-01)
Article
Accés obertThis paper presents the new features of the OmpSs@FPGA framework. OmpSs is a data-flow programming model that supports task nesting and dependencies to target asynchronous parallelism and heterogeneity. OmpSs@FPGA is the ... -
On the resilience of deep learning for reduced-voltage FPGAs
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertDeep Neural Networks (DNNs) are inherently computation-intensive and also power-hungry. Hardware accelerators such as Field Programmable Gate Arrays (FPGAs) are a promising solution that can satisfy these requirements for ... -
Online signature verification systems on a low-cost FPGA
(2022-01-01)
Article
Accés obertThis paper describes three different approaches for the implementation of an online signature verification system on a low-cost FPGA. The system is based on an algorithm, which operates on real numbers using the double-precision ... -
OpenCL-based FPGA accelerator for semi-global approximate string matching using diagonal bit-vectors
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés obertAn FPGA accelerator for the computation of the semi-global Levenshtein distance between a pattern and a reference text is presented. The accelerator provides an important benefit to reduce the execution time of read-mappers ... -
Optimization of OpenCL applications on FPGA
(Universitat Politècnica de Catalunya, 2018-04)
Projecte Final de Màster Oficial
Accés obert
Realitzat a/amb: Barcelona Supercomputing CenterThis document presents an evaluation of OpenCL as a mechanism to exploit FPGA resources. To evaluate it, we show a performance and energy comparison between an Intel Arria 10 and an Intel Xeon E5-2600. We also present a ... -
Performance evaluation and scaling of a multiprocessor architecture emulating complex SNN algorithms
(Springer Verlag, 2010-09)
Article
Accés restringit per política de l'editorialThe performance analysis of an efficient multiprocessor architecture that allows accelerating the emulation of large-scale Spiking Neural Networks (SNNs) is reported. After describing the architecture and the complex SNN ... -
Piano digital: MIDI a S/PDIF
(Universitat Politècnica de Catalunya, 2019-06)
Treball Final de Grau
Accés obertL’objectiu d’aquest projecte és crear un piano funcional fent ús d’una FPGA i un teclat MIDI. Per norma general un teclat MIDI no emet música per si sol; és dependent d’un ordinador i d’un programari específic. En aquest ... -
Planificador de tareas para un modelo de programación de memoria global disjunta para clusters con aceleradores basados en FPGAs
(Universitat Politècnica de Catalunya, 2018-04)
Treball Final de Grau
Accés obertA promising component to improve the performance of High Performance Computing systems is the use of FPGAs. Other ways the performance can be improved is by designing scheduling algorithms for task dependency graphs in a program. -
Plataforma per la programació automàtica del sistema hardware reconfigurable d'una màquina Zynq
(Universitat Politècnica de Catalunya, 2013-12-31)
Projecte/Treball Final de Carrera
Accés obertLas máquinas Zynq son una familia de SoC que integran una FPGA. La intención de este proyecto es automatizar todo el proceso que se requiere para obtener el bitstream a partir de una aplicación escrita en C/C++ con directivas ... -
PMSS: a programmable memory system and scheduler for complex memory patterns
(2014-10)
Article
Accés restringit per política de l'editorialHPC industry demands more computing units on FPGAs, to enhance the performance by using task/data parallelism. FPGAs can provide its ultimate performance on certain kernels by customizing the hardware for the applications. ... -
Port de l'aplicació de bioinformàtica FTDock a la plataforma heterogènia ZYNQ
(Universitat Politècnica de Catalunya, 2016-01)
Treball Final de Grau
Accés obertEn aquest treball es mostra el port de l'aplicació en bioinformàtica FTDock a una plataforma heterogènia formada per un multiprocessador i una FPGA, utilitzant els avantatges que ofereix l'ús d'acceleradors hardware en ...