Ara es mostren els items 151-170 de 198

    • LEGION-based image segmentation by means of spiking neural networks using normalized synaptic weights implemented on a compact scalable neuromorphic architecture 

      Sánchez Rivera, Giovanny; Madrenas Boadas, Jordi; Cosp Vilella, Jordi (2019-01-01)
      Article
      Accés obert
      LEGION (Locally Excitatory, Globally Inhibitory Oscillator Network) topology has demonstrated good capabilities in scene segmentation applications. However, the implementation of LEGION algorithm requires machines with ...
    • Link Layer Optimization of an FPGA-based Transceiver for Free-Space Optical Communication 

      López Cuenca, Carlos (Universitat Politècnica de Catalunya, 2015-07)
      Projecte Final de Màster Oficial
      Accés restringit per decisió de l'autor
      In the relentless pursuit to meet the ever-increasing need for higher communication bandwidths, free-space optical communications shows up as a suitable alternative for particular application areas. Due to the nature of ...
    • Monitorització de bus can amb compact-rio 

      Tost Garcia, Carles (Universitat Politècnica de Catalunya, 2007-02)
      Projecte/Treball Final de Carrera
      Accés restringit per acord de confidencialitat
    • Módulo de una papelera de reciclaje automatizada para cocina 

      González, Iván Alexis Jorge (Universitat Politècnica de Catalunya, 2019-10-31)
      Treball Final de Grau
      Accés restringit per decisió de l'autor
      [CASTELLÀ] Este proyecto persigue automatizar y facilitar la vida a las personas y sus actividades diarias. El objetivo es modelizar la recogida de basura en cada hogar para su mejor evacuación, y si es necesario, también ...
    • Multi-camera PCIe Frame Grabber for ADAS and autonomous driving applications 

      Prats Domènech, Guillem (Universitat Politècnica de Catalunya, 2020-06)
      Treball Final de Grau
      Accés restringit per acord de confidencialitat
    • New Architecture for an Image Compression Algorithm for Embedded Systems 

      Catalán Navarro, Oriol (Universitat Politècnica de Catalunya, 2023-10-18)
      Projecte Final de Màster Oficial
      Accés restringit per acord de confidencialitat
      New, cheaper, and more efficient SoC architectures appear year over year in the market. With this SoCs, HP Inc. develops new products trying to achieve cheaper costs and improve performance compared to previous products ...
    • New Hardware Architecture for Low-Cost Functional Test Systems Applications to HDMI generation 

      Blanch Elias, Marc (Universitat Politècnica de Catalunya, 2011-07-26)
      Projecte/Treball Final de Carrera
      Accés obert
      English: Development of a new test hardware architecture for functional test systems. Development of a proof-of-concept prototype for HDMI generation.
    • Object Recognition using FPGA 

      Irazabal Bengoa, Mikel (Universitat Politècnica de Catalunya, 2011-11-22)
      Projecte Final de Màster Oficial
      Accés obert
      English: Computer vision is the field concerned with the automated processing of images from the real world to extract and interpret information on a real time basis. There are a wide range of tasks such as controlling the ...
    • OmpSs@cloudFPGA: An FPGA task-based programming model with message passing 

      Haro Ruiz, Juan Miguel de; Cano, Rubén; Álvarez Martínez, Carlos; Jiménez González, Daniel; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Abel, François; Ringlein, Burkhard; Weiss, Beat (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Text en actes de congrés
      Accés obert
      Nowadays, a new parallel paradigm for energy-efficient heterogeneous hardware infrastructures is required to achieve better performance at a reasonable cost on high-performance computing applications. Under this new paradigm, ...
    • OmpSs@FPGA framework for high performance FPGA computing 

      Haro Ruiz, Juan Miguel de; Bosch Pons, Jaume; Filgueras Izquierdo, Antonio; Vidal, Miquel; Jiménez González, Daniel; Álvarez Martínez, Carlos; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José (Institute of Electrical and Electronics Engineers (IEEE), 2021-12-01)
      Article
      Accés obert
      This paper presents the new features of the OmpSs@FPGA framework. OmpSs is a data-flow programming model that supports task nesting and dependencies to target asynchronous parallelism and heterogeneity. OmpSs@FPGA is the ...
    • On the resilience of deep learning for reduced-voltage FPGAs 

      Givaki, Kamyar; Salami, Behzad; Hojabr, Reza; Tayaranian, S. M. Reza; Khonsari, Ahmad; Rahmati, Dara; Gorgin, Saeid; Cristal Kestelman, Adrián; Unsal, Osman Sabri (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Text en actes de congrés
      Accés obert
      Deep Neural Networks (DNNs) are inherently computation-intensive and also power-hungry. Hardware accelerators such as Field Programmable Gate Arrays (FPGAs) are a promising solution that can satisfy these requirements for ...
    • Online signature verification systems on a low-cost FPGA 

      Cantó Navarro, Enrique; Ramos Lara, Rafael Ramón; López García, Mariano (2022-01-01)
      Article
      Accés obert
      This paper describes three different approaches for the implementation of an online signature verification system on a low-cost FPGA. The system is based on an algorithm, which operates on real numbers using the double-precision ...
    • OpenCL-based FPGA accelerator for semi-global approximate string matching using diagonal bit-vectors 

      Castells Rufas, David; Marco-Sola, Santiago; Aguado Puig, Quim; Espinosa Morales, Antonio; Moure López, Juan Carlos; Alvarez Martí, Lluc; Moretó Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2021)
      Text en actes de congrés
      Accés obert
      An FPGA accelerator for the computation of the semi-global Levenshtein distance between a pattern and a reference text is presented. The accelerator provides an important benefit to reduce the execution time of read-mappers ...
    • Optimization of OpenCL applications on FPGA 

      Navarro Torrentó, Albert (Universitat Politècnica de Catalunya, 2018-04)
      Projecte Final de Màster Oficial
      Accés obert
      Realitzat a/amb:   Barcelona Supercomputing Center
      This document presents an evaluation of OpenCL as a mechanism to exploit FPGA resources. To evaluate it, we show a performance and energy comparison between an Intel Arria 10 and an Intel Xeon E5-2600. We also present a ...
    • Performance evaluation and scaling of a multiprocessor architecture emulating complex SNN algorithms 

      Sánchez Rivera, Giovanny; Madrenas Boadas, Jordi; Moreno Aróstegui, Juan Manuel (Springer Verlag, 2010-09)
      Article
      Accés restringit per política de l'editorial
      The performance analysis of an efficient multiprocessor architecture that allows accelerating the emulation of large-scale Spiking Neural Networks (SNNs) is reported. After describing the architecture and the complex SNN ...
    • Piano digital: MIDI a S/PDIF 

      Ibáñez Masanés, Guillem (Universitat Politècnica de Catalunya, 2019-06)
      Treball Final de Grau
      Accés obert
      L’objectiu d’aquest projecte és crear un piano funcional fent ús d’una FPGA i un teclat MIDI. Per norma general un teclat MIDI no emet música per si sol; és dependent d’un ordinador i d’un programari específic. En aquest ...
    • Planificador de tareas para un modelo de programación de memoria global disjunta para clusters con aceleradores basados en FPGAs 

      López Mendoza, Juan Antonio (Universitat Politècnica de Catalunya, 2018-04)
      Treball Final de Grau
      Accés obert
      A promising component to improve the performance of High Performance Computing systems is the use of FPGAs. Other ways the performance can be improved is by designing scheduling algorithms for task dependency graphs in a program.
    • Plataforma per la programació automàtica del sistema hardware reconfigurable d'una màquina Zynq 

      Gil Blasco, Eduard (Universitat Politècnica de Catalunya, 2013-12-31)
      Projecte/Treball Final de Carrera
      Accés obert
      Las máquinas Zynq son una familia de SoC que integran una FPGA. La intención de este proyecto es automatizar todo el proceso que se requiere para obtener el bitstream a partir de una aplicación escrita en C/C++ con directivas ...
    • PMSS: a programmable memory system and scheduler for complex memory patterns 

      Hussain, Tassadaq; Haider, Amna; Ayguadé Parra, Eduard (2014-10)
      Article
      Accés restringit per política de l'editorial
      HPC industry demands more computing units on FPGAs, to enhance the performance by using task/data parallelism. FPGAs can provide its ultimate performance on certain kernels by customizing the hardware for the applications. ...
    • Port de l'aplicació de bioinformàtica FTDock a la plataforma heterogènia ZYNQ 

      Josep Fabregó, Marc (Universitat Politècnica de Catalunya, 2016-01)
      Treball Final de Grau
      Accés obert
      En aquest treball es mostra el port de l'aplicació en bioinformàtica FTDock a una plataforma heterogènia formada per un multiprocessador i una FPGA, utilitzant els avantatges que ofereix l'ús d'acceleradors hardware en ...