Exploració per tema "FPGA"
Ara es mostren els items 45-64 de 200
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Data reuse design exploration in OmpSs@FPGA
(Universitat Politècnica de Catalunya, 2019-10-17)
Projecte Final de Màster Oficial
Accés obertIn this thesis, the OmpSs@FPGA tool chain has been extended to try to reduce the overall communication time due to copies of data when it is possible to reuse data already in the BRAM of the accelerators. -
Demonstrating reduced-voltage FPGA-based neural network acceleration for power-efficiency
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Comunicació de congrés
Accés obertThis demo aims to demonstrate undervolting below the nominal level set by the vendor for off-the-shelf FPGAs running Deep Neural Networks (DNNs), to achieve power-efficiency. FPGAs are becoming popular [1-4], thanks to ... -
Desarrollo de una plataforma de trabajo para la investigación
(Universitat Politècnica de Catalunya, 2010-06-22)
Projecte/Treball Final de Carrera
Accés obert -
Desenvolupament d'un Time to Digital Converter en una FPGA per la lectura de fotosensors de baixa lluminositat
(Universitat Politècnica de Catalunya, 2024-01-29)
Treball Final de Grau
Accés obert
Realitzat a/amb: Institut de Ciències del CosmosEn aquest document es presenta un circuit dedicat a la digitalització de la lectura del senyal capturat per fotosensors de baixa lluminositat per imatge mèdica, en particular, per un escàner de tomografia per emissió ... -
Desenvolupament d’un laboratori remot per la programació de Field Programmable Gate Arrays (FPGAs)
(Universitat Politècnica de Catalunya, 2022-07-12)
Treball Final de Grau
Accés obertEn aquest projecte el que es vol assolir com a resultat final és la implementació d’un laboratori remot per la programació de FPGAs. L'accés es du a terme via web, per tant una part molt important en aquest projecte és ... -
Desenvolupament en una FPGA d'un transmissor basat en una arquitectura LINC:
(Universitat Politècnica de Catalunya, 2010-07-23)
Treball Final de Grau
Accés obert -
Design and Development of an FPGA-based Medical EIS System
(Universitat Politècnica de Catalunya, 2022-10-27)
Projecte Final de Màster Oficial
Accés obertElectrical impedance spectroscopy is a powerful technique which can be used to characterize properties of many materials, including biological tissues. In medical applications, it is typically used as a complementary tool ... -
Design and implementation of a data acquisition and transmission system based on configurable hardware
(Universitat Politècnica de Catalunya, 2018-10)
Projecte Final de Màster Oficial
Accés restringit per decisió de l'autorThe aim of this project is to find a practical solution for high speed data transfers rate systems. The goal of the project is to design and develop a functional prototype able to acquire data from an analogue source and ... -
Design and implementation of a low-cost FPGA-Based bioimpedance measurement system
(Universitat Politècnica de Catalunya, 2014-10-24)
Projecte Final de Màster Oficial
Accés obertCurrently, many impedance measurement systems have been developed. This project details the design, implementation and characterization of a FPGA-based bioimpedance measurement system, whose goal is obtaining good performance ... -
Design and implementation of an architecture-aware hardware runtime for heterogeneous systems
(Barcelona Supercomputing Center, 2020-05)
Text en actes de congrés
Accés obertParallel computing has become the norm to gain performance in multicore and heterogeneous systems. Many programming models allow to exploit this parallelism with easy to use tools. In this work we focus on task-based ... -
Design and implementation of an architecture-aware hardware runtime for heterogeneous systems
(Universitat Politècnica de Catalunya, 2020-06-30)
Projecte Final de Màster Oficial
Accés obertIn order to keep accelerating applications, it is a common trend to use heterogeneous systems with specialized hardware. They offer the best trade-off in performance and power consumption at the cost of programmability. ... -
Design and implementation of an ARMv4 tightly coupled multicore in VHDL and validation on a FPGA
(Universitat Politècnica de Catalunya / Technische Universität Berlin, 2012-07-09)
Projecte/Treball Final de Carrera
Accés obert[ANGLÈS] On one hand, few years ago increasing the clock speed was the preferred tactic by manufacturers to gradually increase the performance of computers. However, from certain speeds there are some limitations. Some ... -
Design and implementation of an UDP/IP Ethernet hardware protocol stack for FPGA based Systems
(Universitat Politècnica de Catalunya, 2019-01-17)
Projecte Final de Màster Oficial
Accés obert
Realitzat a/amb: Universitat de Barcelona. Institut de Ciències del CosmosThe main objective of the thesis has been the design and implementation of a complete UDP/IP Ethernet stack that allow us the connection and use of networks by any FPGA device. The stack has been designed around Ethernet, ... -
Design and integration of a multipurpose on board computer for nanosatellites with SDR communications
(Universitat Politècnica de Catalunya, 2019-10-30)
Projecte Final de Màster Oficial
Accés obert -
Design and test of a neural microprocessor
(Universitat Politècnica de Catalunya, 2022-06-28)
Treball Final de Grau
Accés obertEn aquest projecte, es dissenya un microprocessador neuronal per ser implementat en FPGAs. Aquesta tecnologia consisteix en un processador softcore basat en RISC-V descrit amb SystemVerilog que s'utilitza per controlar un ... -
Design of a modular instrument with reconfigurable Input/Output for test and measurement
(Universitat Politècnica de Catalunya, 2018-02)
Projecte Final de Màster Oficial
Accés restringit per acord de confidencialitatThe purpose of this Master Thesis is the study of the capabilities offered by the National Instruments sbRIO-9651 System-On-Module, to determine if it?s suitable for the implementation of automatic test equipment instruments. ... -
Design of an image acquisition and processing system using configurable devices
(Universitat Politècnica de Catalunya, 2021-06)
Projecte Final de Màster Oficial
Accés obertThis thesis consists of the evaluation of the possibility to implement a Neural Network in an FPGA instead on the more used GPU. Theoretically, an FPGA is a better choice in terms of processing power, latency, or flexibility ... -
Design, implementation, and validation of probability distributions generators in FPGA
(Universitat Politècnica de Catalunya, 2021-05-25)
Projecte Final de Màster Oficial
Accés restringit per acord de confidencialitat -
Design, implementation, and verification of an FPGA-based control system for a permanent-magnet motor drive built upon a three-phase four-level active-clamped inverter
(Universitat Politècnica de Catalunya, 2015-05)
Projecte Final de Màster Oficial
Accés obert[ANGLÈS] The present work summarizes the work and knowledge acquired by the author during its Master’s Thesis in the Research Group in Power Electronics, GREP. The development is based on the Multilevel Active-Clamped (MAC) ... -
Designing avionics for lasers & optoelectronics
(Universitat Politècnica de Catalunya, 2022-04-29)
Comunicació de congrés
Accés obertUnlike imagery-based Earth observation (EO) which has become very widely and cheaply available, gravity sensing EO has not yet emerged from its fundamental science roots. The challenge therefore is to develop gravity sensing ...