Exploració per tema "logic design"

Ara es mostren els items 1-2 de 2

    • Novel redundant logic design for noisy low voltage scenarios 

      García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2013)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      The concept worked in this paper named Turtle Logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging CMOS technologies and beyond, where the thermal noise could be ...

    • Variability-tolerant memristor-based ratioed logic in crossbar array 

      Escudero López, Manuel; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja; Vourkas, Ioannis (Institute of Electrical and Electronics Engineers (IEEE), 2018)
      Text en actes de congrés
      Accés obert
      The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this de- vice technology, with several emerging applications including that of logic circuits. Several ...