Exploració per tema "Ordinadors -- Memòries"
Ara es mostren els items 1-20 de 23
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An hybrid eDRAM/SRAM macrocell to implement first-level data caches
(Association for Computing Machinery (ACM), 2009)
Text en actes de congrés
Accés restringit per política de l'editorialSRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are ... -
Conflict-free strides for vectors in matched memories
(1991-12)
Article
Accés obertAddress transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free access to one family of strides in vector processors with matched memories. The paper extends these ... -
Cost-effective compiler directed memory prefetching and bypassing
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Text en actes de congrés
Accés obertEver increasing memory latencies and deeper pipelines push memory farther from the processor. Prefetching techniques aim is to bridge these two gaps by fetching data in advance to both the L1 cache and the register file. ... -
CRAID: Online RAID upgrades using dynamic hot data reorganization
(USENIX Association, 2014)
Text en actes de congrés
Accés obertCurrent algorithms used to upgrade RAID arrays typically require large amounts of data to be migrated, even those that move only the minimum amount of data required to keep a balanced data load. This paper presents CRAID, ... -
Distributing orthogonal redundancy on adaptive disk arrays
(Springer, 2008)
Text en actes de congrés
Accés restringit per política de l'editorialWhen upgrading storage systems, the key is migrating data from old storage subsystems to the new ones for achieving a data layout able to deliver high performance I/O, increased capacity and strong data availability while ... -
ECHOFS: a scheduler-guided temporary filesystem to leverage node-local NVMS
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertThe growth in data-intensive scientific applications poses strong demands on the HPC storage subsystem, as data needs to be copied from compute nodes to I/O nodes and vice versa for jobs to run. The emerging trend of adding ... -
Freezing time emulating new and faster devices with virtual machines
(Springer, 2020)
Article
Accés obertRecent proposals of emerging data storage devices make it necessary to reevaluate all levels of the storage hierarchy to optimize the software stack performance. However, these new devices are not always widely available ... -
Freezing Time: a new approach for emulating fast storage devices using VM
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertRecently we are seeing a considerable effort from both academy and industry in proposing new technologies for storage devices. Often these devices are not readily available for evaluation and methods to allow performing ... -
HetFS: A heterogeneous file system for everyone
(Springer, 2017)
Text en actes de congrés
Accés obertStorage devices have been getting more and more diverse during the last decade. The advent of SSDs made it painfully clear that rotating devices, such as HDDs or magnetic tapes, were lacking in regards to response time. ... -
Implementació en HDL d'un arbre binari de cerca auto-balancejat
(Universitat Politècnica de Catalunya, 2017-06-27)
Projecte/Treball Final de Carrera
Accés obert
Realitzat a/amb: Barcelona Supercomputing CenterAmb la proliferació de les arquitectures multi-core i many-core, s’han emprat molts esforços en l’especificació i la implementació de nous models de programació, que facilitessin als desenvolupadors de programari la ... -
Improving cache Behavior in CMP architectures throug cache partitioning techniques
(Universitat Politècnica de Catalunya, 2010-03-19)
Tesi
Accés obertThe evolution of microprocessor design in the last few decades has changed significantly, moving from simple inorder single core architectures to superscalar and vector architectures in order to extract the maximum available ... -
Increasing the number of strides for conflict-free vector access
(1992-05)
Article
Accés obertAddress transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free vector access for some strides in vector processors with multi-module memories. In this paper, we ... -
ITCA: Inter-Task Conflict-Aware CPU accounting for CMP
(2010)
Text en actes de congrés
Accés obertChip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ... -
Light NUCA: a proposal for bridging the inter-cache latency gap
(IEEE Computer Society, 2009)
Comunicació de congrés
Accés obertTo deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between them and fast L1 caches (inter-cache latency gap). ... -
Memorias SRAM en "Hardware Description Language (HDL)" para una plataforma de simulación de codigos en HDL.
(Universitat Politècnica de Catalunya, 2010-04-16)
Treball Final de Grau
Accés obert -
Memory Dependence Prediction Methods Study and Improvement Proposals
(Universitat Politècnica de Catalunya, 2011-03-28)
Projecte Final de Màster Oficial
Accés obertEnglish: Nowadays, most modern high performance processors employ out-of-order (O3) execution. In these processors, instructions are executed as soon as possible increasing in this way the instruction level parallelism ... -
Performance impacts with reliable parallel file systems at exascale level
(Springer, 2015)
Text en actes de congrés
Accés restringit per política de l'editorialThe introduction of Exascale storage into production systems will lead to an increase on the number of storage servers needed by parallel file systems. In this scenario, parallel file system designers should move from the ... -
Reducing fetch architecture complexity using procedure inlining
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertFetch engine performance is seriously limited by the branch prediction table access latency. This fact has lead to the development of hardware mechanisms, like prediction overriding, aimed to tolerate this latency. However, ... -
Reliability-aware memory design using advanced reconfiguration mechanisms
(Universitat Politècnica de Catalunya, 2015-11-16)
Tesi
Accés obertFast and Complex Data Memory systems has become a necessity in modern computational units in today's integrated circuits. These memory systems are integrated in form of large embedded memory for data manipulation and ... -
Sesquickselect: One and a half pivots for cache-efficient selection
(Curran, 2019)
Text en actes de congrés
Accés obertBecause of unmatched improvements in CPU performance, memory transfers have become a bottleneck of program execution. As discovered in recent years, this also affects sorting in internal memory. Since partitioning around ...
