Exploració per tema "Multiprocessing systems"

Ara es mostren els items 1-20 de 54

    • A decoupled KILO-instruction processor 

      Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; González García, Rubén; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2006)
      Text en actes de congrés
      Accés obert
      Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elusive goal. Traditional processors are ...

    • A dependency-aware task-based programming environment for multi-core architectures 

      Pérez Cáncer, Josep Maria; Badia Sala, Rosa Maria; Labarta Mancho, Jesús José (2008)
      Text en actes de congrés
      Accés obert
      Parallel programming on SMP and multi-core architectures is hard. In this paper we present a programming model for those environments based on automatic function level parallelism that strives to be easy, flexible, portable, ...

    • A flexible heterogeneous multi-core architecture 

      Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; Cazorla, Francisco; González García, Rubén; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2007)
      Text en actes de congrés
      Accés obert
      Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a challenge as application mixes in this ...

    • A highly scalable parallel implementation of H.264 

      Azevedo, Arnaldo; Juurlink, Ben; Meenderinck, Cor; Terechko, Andrei; Hoogerbrugge, Jan; Álvarez Mesa, Mauricio; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2011)
      Article
      Accés obert
      Developing parallel applications that can harness and efficiently use future many-core architectures is the key challenge for scalable computing systems. We contribute to this challenge by presenting a parallel implementation ...

    • A systolic algorithm for the fast computation of the connected components of a graph 

      Núñez, Fernando J.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1988)
      Text en actes de congrés
      Accés obert
      The authors consider the description of a systolic algorithm to solve the connected-component problem. It is executed in a ring topology with N processors, requiring O(Nlog N) time without regard to the graph's sparsity. ...

    • Access to vectors in multi-module memories 

      Valero Cortés, Mateo; Peiron Guàrdia, Montse; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 1994)
      Text en actes de congrés
      Accés obert
      The poor bandwidth obtained from memory when conflicts arise in the modules or in the interconnection network degrades the performance of computers. Address transformation schemes, such as interleaving, skewing and linear ...

    • Adapting cache partitioning algorithms to pseudo-LRU replacement policies 

      Kedzierski, Kamil; Moretó Planas, Miquel; Cazorla, Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2010)
      Text en actes de congrés
      Accés obert
      Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache partitioning algorithms proposed so far assume Least ...

    • AMMC: advance multi-core memory controller 

      Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Comunicació de congrés
      Accés obert
      In this work, we propose an efficient scheduler and intelligent memory manager known as AMMC (Advanced Multi-Core Memory Controller), which proficiently handles data movement and computational tasks. The proposed AMMC ...

    • An abstraction methodology for the evaluation of multi-core multi-threaded architectures 

      Zilan, Ruken; Verdú Mulà, Javier; García Vidal, Jorge; Nemirovsky, Mario; Milito, Rodolfo; Valero Cortés, Mateo (IEEE Computer Society Publications, 2011)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      As the evolution of multi-core multi-threaded processors continues, the complexity demanded to perform an extensive trade-off analysis, increases proportionally. Cycle-accurate or trace-driven simulators are too slow to ...

    • An open benchmark implementation for multi-CPU multi-GPU pedestrian detection in automotive systems 

      Trompouki, Matina M.; Kosmidis, Leonidas; Navarro, Nacho (IEEE, 2017-12-14)
      Comunicació de congrés
      Accés obert
      Modern and future automotive systems incorporate several Advanced Driving Assistance Systems (ADAS). Those systems require significant performance that cannot be provided with traditional automotive processors and programming ...

    • Analysis and simulation of multiplexed single-bus networks with and without buffering 

      Llaberia Griñó, José M.; Valero Cortés, Mateo; Herrada Lillo, Enrique; Labarta Mancho, Jesús José (Institute of Electrical and Electronics Engineers (IEEE), 1985)
      Text en actes de congrés
      Accés obert
      Performance issues of a single-bus interconnection network for multiprocessor systems, operating in a multiplexed way, are presented in this paper. Several models are developed and used to allow system performance evaluation. ...

    • CATA: Criticality aware task acceleration for multicore processors 

      Castillo, Emilio; Moretó Planas, Miquel; Casas, Marc; Álvarez Martí, Lluc; Vallejo, Enrique; Chronaki, Kallia; Badia Sala, Rosa Maria; Bosque Orero, José Luis; Beivide Palacio, Julio Ramón; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Text en actes de congrés
      Accés obert
      Managing criticality in task-based programming models opens a wide range of performance and power optimization opportunities in future manycore systems. Criticality aware task schedulers can benefit from these opportunities ...

    • CellMT: A cooperative multithreading library for the Cell/B.E. 

      Beltran Querol, Vicenç; Carrera Pérez, David; Torres Viñals, Jordi; Ayguadé Parra, Eduard (IEEE Computer Society Publications, 2009-12-16)
      Text en actes de congrés
      Accés obert
      The Cell BE processor has proved that heterogeneous multi-core systems can provide a huge computational power with high efficiency for a wide range of applications. The simple design of the computational units and the use ...

    • Cost-conscious strategies to increase performance of numerical programs on agressive VLIW architectures 

      López Álvarez, David; Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard (2001-10)
      Article
      Accés obert
      Loops are the main time-consuming part of numerical applications. The performance of the loops is limited either by the resources offered by the architecture or by recurrences in the computation. To execute more operations ...

    • CPU accounting in CMP processors 

      Luque, Carlos; Moretó Planas, Miquel; Cazorla, Francisco; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo (2009-01)
      Article
      Accés obert
      Chip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ...

    • Dcache Warn: an I-fetch policy to increase SMT efficiency 

      Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo; Fernandez Garcia, Enrique (Institute of Electrical and Electronics Engineers (IEEE), 2004)
      Text en actes de congrés
      Accés obert
      Simultaneous multithreading (SMT) processors increase performance by executing instructions from multiple threads simultaneously. These threads share the processor's resources, but also compete for them. In this environment, ...

    • DReAM: Per-task DRAM energy metering in multicore systems 

      Liu, Qixiao; Moretó Planas, Miquel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (Springer, 2014)
      Text en actes de congrés
      Accés obert
      Interaction across applications in DRAM memory impacts its energy consumption. This paper makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations, ...

    • Dynamic-vector execution on a general purpose EDGE chip multiprocessor 

      Duric, Milovan; Palomar Pérez, Óscar; Smith, Aaron; Stanic, Milan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo; Burger, Doug; Veidenbaum, Alexander V (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      This paper proposes a cost-effective technique that morphs the available cores of a low power chip multiprocessor (CMP) into an accelerator for data parallel (DLP) workloads. Instead of adding a special-purpose vector ...

    • DYON: Managing a new scheduling class to improve system performance in multicore systems 

      Nou Castell, Ramon; Giralt Celiméndiz, Jacobo; Cortés, Toni (Springer, 2013)
      Text en actes de congrés
      Accés obert
      Due to the increase in the number of available cores in current systems, plenty of system software starts to use some of these cores to perform tasks that will help optimize the application behaviour. Unfortunately, current ...

    • Efficient development of high performance data analytics in Python 

      Álvarez Cid-Fuentes, Javier; Alvarez, Pol; Amela Milian, Ramon; Ishii, Kuninori; Morizawa, Rafael K.; Badia Sala, Rosa Maria (Elsevier, 2020-10)
      Article
      Accés obert
      Our society is generating an increasing amount of data at an unprecedented scale, variety, and speed. This also applies to numerous research areas, such as genomics, high energy physics, and astronomy, for which large-scale ...