Exploració per tema "Multiple data stream architectures"

Ara es mostren els items 1-2 de 2

    • Comparing last-level cache designs for CMP architectures 

      Vega, Augusto; Rico Carro, Alejandro; Cabarcas, Felipe; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2010)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      The emergence of hardware accelerators, such as graphics processing units (GPUs), has challenged the interaction between processing elements (PEs) and main memory. In architectures like the Cell/B.E. or GPUs, the PEs ...

    • DReAM: An approach to estimate per-Task DRAM energy in multicore systems 

      Liu, Qixiao; Moretó Planas, Miquel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (2016-12)
      Article
      Accés obert
      Accurate per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is ...