Ara es mostren els items 1-20 de 35

    • A case for acoustic wave detectors for soft-errors 

      Upasani, Gaurang; Vera Rivera, Francisco Javier; González Colás, Antonio María (2016-01-01)
      Article
      Accés restringit per política de l'editorial
      The continuing decrease in dimensions and operating voltage of transistors has increased their sensitivity against radiation phenomena, making soft errors an important challenge in future microprocessors. New techniques ...
    • A case for code-representative microbenchmarks 

      Bulla, Calvin; Moretó Planas, Miquel (Barcelona Supercomputing Center, 2017-05-04)
      Text en actes de congrés
      Accés obert
      Microbenchmarks are fundamental in the design of a microarchitecture. They allow rapid evaluation of the system, while incurring little exploration overhead. One key design aspect is the thermal design point (TDP), the ...
    • Analyzing and improving hardware modeling of Accel-Sim 

      Huerta Gañán, Rodrigo; Abaie Shoushtary, Mojtaba; González Colás, Antonio María (2023-10)
      Report de recerca
      Accés obert
      GPU architectures have become popular for executing generalpurpose programs. Their many-core architecture supports a large number of threads that run concurrently to hide the latency among dependent instructions. In modern ...
    • Archexplorer for automatic design space exploration 

      Desmet, V.; Girbal, Sylvain; Ramírez Bellido, Alejandro; Temam, Olivier; Vega, Augusto (2010-09-09)
      Article
      Accés obert
      Growing architectural complexity and stringent time-to-market constraints suggest the need to move architecture design beyond parametric exploration to structural exploration. ArchExplorer is a Web-based permanent and open ...
    • Automatic microarchitectural pipelining 

      Galcerán Oms, Marc; Cortadella, Jordi; Bufistov, Dmitry; Kishinevsky, Michael (Institute of Electrical and Electronics Engineers (IEEE), 2010)
      Text en actes de congrés
      Accés obert
      This paper presents a method for automatic microarchitectural pipelining of systems with loops. The original specification is pipelined by performing provably-correct transformations including conversion to a synchronous ...
    • Characterizing fault propagation in safety-critical processor designs 

      Espinosa, Jaime; Hernandez, Carles; Abella Ferrer, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2015)
      Text en actes de congrés
      Accés obert
      Achieving reduced time-to-market in modern electronic designs targeting safety critical applications is becoming very challenging, as these designs need to go through a certification step that introduces a non-negligible ...
    • Compiler analysis for trace-level speculative multithreaded architectures 

      Molina Clemente, Carlos; González Colás, Antonio María; Tubella Murgadas, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2005)
      Text en actes de congrés
      Accés obert
      Trace-level speculative multithreaded processors exploit trace-level speculation by means of two threads working cooperatively. One thread, called the speculative thread, executes instructions ahead of the other by speculating ...
    • Correct-by-construction microarchitectural pipelining 

      Kam, Timothy; Kishinevsky, Michael; Cortadella, Jordi; Galcerán Oms, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2008)
      Text en actes de congrés
      Accés obert
      This paper presents a method for correct-by-construction microarchitectural pipelining that handles cyclic systems with dependencies between iterations. Our method combines previously known bypass and retiming transformations ...
    • Decision Support Database Management System Acceleration Using Vector Processor 

      Hayes, Timothy (Universitat Politècnica de Catalunya, 2011-09-20)
      Projecte Final de Màster Oficial
      Accés obert
      English: This work takes a top-down approach to accelerating decision support systems (DSS) on x86-64 microprocessors using true vector ISA extensions. First, a state of art DSS database management system (DBMS) is pro ...
    • Design of energy-efficient vector units for in-order cores 

      Stanić, Milan (Universitat Politècnica de Catalunya, 2017-01-31)
      Tesi
      Accés obert
      In the last 15 years, power dissipation and energy consumption have become crucial design concerns for almost all computer systems. Technology feature size scaling leads to higher power density and therefore to complex and ...
    • Design, implementation and evaluation of an out-of-order instruction queue based on a parameterizable model 

      Iznardo Ruiz, Alejandro (Universitat Politècnica de Catalunya, 2023-01-24)
      Projecte Final de Màster Oficial
      Accés restringit per decisió de l'autor
    • Dynamically controlled resource allocation in SMT processors 

      Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo; Fernandez Prieto, Enrique (Institute of Electrical and Electronics Engineers (IEEE), 2004)
      Text en actes de congrés
      Accés obert
      SMT processors increase performance by executing instructions from several threads simultaneously. These threads use the resources of the processor better by sharing them but, at the same time, threads are competing for ...
    • DynAMO: Improving parallelism through dynamic placement of atomic memory operations 

      Soria Pardos, Víctor; Armejach Sanosa, Adrià; Mück, Tiago; Suárez Gracía, Dario; Joao, Jose A.; Rico, Alejandro; Moretó Planas, Miquel (Association for Computing Machinery (ACM), 2023)
      Text en actes de congrés
      Accés obert
      With increasing core counts in modern multi-core designs, the overhead of synchronization jeopardizes the scalability and efficiency of parallel applications. To mitigate these overheads, modern cache-coherent protocols ...
    • Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor 

      Gibert Codina, Enric; Sánchez Navarro, Jesús; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2002)
      Text en actes de congrés
      Accés obert
      Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functional units and the data cache are partitioned, ...
    • Efficient interconnects for clustered microarchitectures 

      Parcerisa Bundó, Joan Manuel; Sahuquillo, Julio; González Colás, Antonio María; Duato, José (Institute of Electrical and Electronics Engineers (IEEE), 2002)
      Text en actes de congrés
      Accés obert
      Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we investigate the design of on-chip interconnection ...
    • Empowering a helper cluster through data-width aware instruction selection policies 

      Unsal, Osman Sabri; Ergin, Oguz; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society, 2006)
      Text en actes de congrés
      Accés obert
      Narrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. On the other hand, clustering mechanisms enable cost- and performance-effective scaling of processor ...
    • Exploiting pseudo-schedules to guide data dependence graph partitioning 

      Aleta Ortega, Alexandre; Codina Viñas, Josep M.; Sánchez Navarro, F. Jesús; González Colás, Antonio María; David, Kaeli (Institute of Electrical and Electronics Engineers (IEEE), 2002)
      Text en actes de congrés
      Accés obert
      This paper presents a new modulo scheduling algorithm for clustered microarchitectures. The main feature of the proposed scheme is that the assignment of instructions to clusters is done by means of graph partitioning ...
    • Flexible compiler-managed L0 buffers for clustered VLIW processors 

      Gibert Codina, Enric; Sánchez Navarro, F. Jesús; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2003)
      Text en actes de congrés
      Accés obert
      Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as clusters. A cluster usually consists of a ...
    • Frontend frequency-voltage adaptation for optimal energy-delay/sup 2/ 

      Grigorios, Magklis; González González, José; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2004)
      Text en actes de congrés
      Accés obert
      In this paper, we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines the benefits of both clustering and globally asynchronous locally synchronous (GALS) designs. We also present a mechanism ...
    • GMX: Instruction set extensions for fast, scalable, and efficient genome sequence alignment 

      Doblas Font, Max; Lostes Cazorla, Oscar; Aguado Puig, Quim; Cebry, Nicholas; Fontova Muste, Pau; Batten, Christopher; Marco Sola, Santiago; Moretó Planas, Miquel (Association for Computing Machinery (ACM), 2023)
      Text en actes de congrés
      Accés obert
      Sequence alignment remains a fundamental problem in computer science with practical applications ranging from pattern matching to computational biology. The ever-increasing volumes of genomic data produced by modern DNA ...