Exploració per tema "Memòria cau"

Ara es mostren els items 1-20 de 109

    • 8T SRAM Cell with Open Defects under Voltage and Timing Variations 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan; Castillo Muñoz, Raul (2011)
      Text en actes de congrés
      Accés obert

    • A comparison of cache hierarchies for SMT processors 

      Suárez Gracía, Dario; Monreal Arnal, Teresa; Viñals Yúfera, Víctor (Universidad de La Laguna. Servicio de Publicaciones, 2011)
      Text en actes de congrés
      Accés obert
      In the multithread and multicore era, programs are forced to share part of the processor structures. On one hand, the state of the art in multithreading describes how efficiently manage and distribute inner resources such ...

    • A confidence assessment of WCET estimates for software time randomized caches 

      Benedicte Illescas, Pedro; Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Text en actes de congrés
      Accés obert
      Obtaining Worst-Case Execution Time (WCET) estimates is a required step in real-time embedded systems during software verification. Measurement-Based Probabilistic Timing Analysis (MBPTA) aims at obtaining WCET estimates ...

    • A decoupled KILO-instruction processor 

      Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; González García, Rubén; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2006)
      Text en actes de congrés
      Accés obert
      Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elusive goal. Traditional processors are ...

    • A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness 

      Cook, Henry; Moretó Planas, Miquel; Bird, Sarah L.; Dao, Khanh; Patterson, David; Asanovic, Krste (ACM, 2013)
      Text en actes de congrés
      Accés obert
      Computing workloads often contain a mix of interactive, latency-sensitive foreground applications and recurring background computations. To guarantee responsiveness, interactive and batch applications are often run on ...

    • A two level load/store queue based on execution locality 

      Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; Cazorla, Francisco; González García, Rubén; Veidenbaum, Alexander V; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
      Text en actes de congrés
      Accés obert
      Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be increasingly limited by the remaining sequential ...

    • Access to vectors in multi-module memories 

      Valero Cortés, Mateo; Peiron Guàrdia, Montse; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 1994)
      Text en actes de congrés
      Accés obert
      The poor bandwidth obtained from memory when conflicts arise in the modules or in the interconnection network degrades the performance of computers. Address transformation schemes, such as interleaving, skewing and linear ...

    • ADAM : an efficient data management mechanism for hybrid high and ultra-low voltage operation caches 

      Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo (2012)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Semiconductor technology evolution enables the design of ultra-low-cost chips (e.g., below 1 USD) required for new market segments such as environment, urban life and body monitoring, etc. Recently, hybrid-operation (high ...

    • Adapting cache partitioning algorithms to pseudo-LRU replacement policies 

      Kedzierski, Kamil; Moretó Planas, Miquel; Cazorla, Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2010)
      Text en actes de congrés
      Accés obert
      Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache partitioning algorithms proposed so far assume Least ...

    • Adaptive runtime-assisted block prefetching on chip-multiprocessors 

      García Flores, Víctor; Rico Carro, Alejandro; Villavieja Prados, Carlos; Carpenter, Paul Matthew; Navarro, Nacho; Ramirez, Alex (2016-04-29)
      Article
      Accés obert
      Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the ...

    • An adaptive controller to save dynamic energy in LP-NUCA 

      Suárez Gracía, Dario; Monreal Arnal, Teresa; Viñals Yúfera, Víctor (Universidad de La Laguna. Servicio de Publicaciones, 2011)
      Text en actes de congrés
      Accés obert
      Portable devices often demand powerful processors to run computing intensive applications, such as video playing or gaming, and ultra low en-ergy consumption to extend device uptime. Such con-flicting requirements are hard ...

    • An analytical model for Loc/ID mappings caches 

      Coras, Florin-Tudorel; Domingo Pascual, Jordi; Lewis, Darrel; Cabellos Aparicio, Alberto (2016-02)
      Article
      Accés obert
      Concerns regarding the scalability of the interdomain routing have encouraged researchers to start elaborating a more robust Internet architecture. While consensus on the exact form of the solution is yet to be found, the ...

    • An energy-efficient memory unit for clustered microarchitectures 

      Bieschewski, Stefan; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (2016-08-01)
      Article
      Accés obert
      Whereas clustered microarchitectures themselves have been extensively studied, the memory units for these clustered microarchitectures have received relatively little attention. This article discusses some of the inherent ...

    • Analyzing long-term access locality to find ways to improve distributed storage systems 

      Miranda Bueno, Alberto; Cortés, Toni (2012)
      Text en actes de congrés
      Accés obert
      An efficient design for a distributed filesystem originates from a deep understanding of common access patterns and user behavior which is obtained through a deep analysis of traces and snapshots. In this paper we analyze ...

    • APPLE: Adaptive performance-predictable low-energy caches for reliable hybrid voltage operation 

      Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2013)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Semiconductor technology evolution enables the design of resource-constrained battery-powered ultra-low-cost chips required for new market segments such as environment, urban life and body monitoring. Caches have been shown ...

    • Author retrospective for the dual data cache 

      González Colás, Antonio María; Aliagas Castell, Carles (Association for Computing Machinery (ACM), 2014)
      Capítol de llibre
      Accés obert
      In this paper we present a retrospective on our paper published in ICS 1995, which to best of our knowledge was the first paper that introduced the concept of a cache memory with multiple subcaches, each tuned for a different ...

    • Automatic safe data reuse detection for the WCET analysis of systems with data caches 

      Segarra Flor, Juan; Cortadella, Jordi; Gran Tejero, Rubén; Viñals Yúfera, Victor (Institute of Electrical and Electronics Engineers (IEEE), 2020-10-19)
      Article
      Accés obert
      Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges in real-time systems. Caches exploit the inherent reuse properties of programs, temporarily storing certain memory contents ...

    • Autonomic content delivery network service 

      Velasco Esteban, Luis Domingo; Gifré Renom, Lluís; Ruiz Ramírez, Marc (2019)
      Text en actes de congrés
      Accés obert
      We focus on a use case where a virtualized Content Delivery Network (CDN) service autonomously adapts to the load by requesting the instantiation of new VMs in selected leaf cache nodes, as well as by ...

    • Branch classification to control instruction fetch in simultaneous multithreaded architectures 

      Knijnenburg, Peter M.W.; Ramírez Bellido, Alejandro; Latorre Salinas, Fernando; Larriba Pey, Josep; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
      Text en actes de congrés
      Accés obert
      In simultaneous multithreaded architectures many separate threads are running concurrently, sharing processor resources, thereby realizing a high utilization rate of the available hardware. However, this also implies that ...

    • Cache-aware load balancing vs. cooperative caching for distributed search engines 

      Domínguez Sal, David; Pérez Casany, Marta; Larriba Pey, Josep (IEEE Computer Society Publications, 2009-06-25)
      Text en actes de congrés
      Accés obert
      In this paper we study the performance of a distributed search engine from a data caching point of view. We compare and combine two different approaches to achieve better hit rates: (a) send the queries to the node which ...