Exploració per tema "Logic synthesis"

Ara es mostren els items 1-8 de 8

    • A hierarchical mathematical model for automatic pipelining and allocation using elastic systems 

      Cortadella, Jordi; Petit Silvestre, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2018)
      Text en actes de congrés
      Accés obert
      The advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical ...

    • A recursive paradigm to solve boolean relations 

      Baneres, David; Cortadella, Jordi; Kishinevsky, Michael (Institute of Electrical and Electronics Engineers (IEEE), 2009-04)
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      Accés obert
      A Boolean relation can specify some types of flexibility of a combinational circuit that cannot be expressed with don't cares. Several problems in logic synthesis, such as Boolean decomposition or multilevel minimization, ...

    • Circuit topology and synthesis flow co-design for the development of computational ReRAM 

      Fernandez Hernandez, Carlos; Vourkas, Ioannis; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2022)
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      Emerging memory technologies will play a decisive role in the quest for more energy-efficient computing systems. Computational ReRAM structures based on resistive switching devices (memristors) have been explored for ...

    • Lazy transition systems and asynchronous circuits synthesis with relative timing assumptions 

      Cortadella, Jordi; Kishinevsky, Michael; Burns, Steven M.; Kondratyev, Alex; Lavagno, Luciano; Stevens, Kenneth S.; Taubin, Alexander; Yakovlev, Alex (2002-02)
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      Accés obert
      This paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions systems as a new computational model to represent the timing information required for synthesis. The notion of laziness ...

    • Logic synthesis for manufacturability considering regularity and lithography printability 

      Machado, Lucas; Dal Bem, Vinicius; Moll Echeto, Francisco de Borja; Gómez Fernández, Sergio; Ribas, Renato P.; Reis, André Inácio (IEEE Computer Society Publications, 2013)
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      Accés restringit per política de l'editorial
      This paper presents a novel yield model for integrated circuits manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the printability of IC layouts, ...

    • RTL synthesis: From logic synthesis to automatic pipelining 

      Cortadella, Jordi; Galcerán Oms, Marc; Kishinevsky, Mike; Sapatnekar, Sachin S. (2015-11-01)
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      Accés obert
      Design automation has been one of the main propellers of the semiconductor industry with logic synthesis being one of the core technologies in this field. This article reviews the evolution of logic synthesis until the ...

    • Support-reducing decomposition for FPGA mapping 

      Machado, Lucas; Cortadella, Jordi (2020-01)
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      Accés obert
      Decomposition is a technology-independent process, in which a large complex function is broken into smaller, less complex functions. The costs of two-level or factored-form representations (cubes and literals) are used in ...

    • Synthesis of asynchronous controllers using integer linear programming 

      Carmona Vargas, Josep; Colom Piazuelo, José Manuel; Cortadella, Jordi; García-Vallés, Fernando (2006-09)
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      Accés obert
      A novel strategy for the logic synthesis of asynchronous control circuits is presented. It is based on the structural theory of Petri nets and integer linear programming. Techniques that are capable of checking implementability ...