Exploració per tema "Integrated circuit modelling"

Ara es mostren els items 1-3 de 3

    • Analysis and modelling of parasitic substrate coupling in CMOS circuits 

      Aragonès Cervera, Xavier; Moll Echeto, Francisco de Borja; Roca Adrover, Miquel; Rubio Sola, Jose Antonio (1995-10)
      Article
      Accés restringit per política de l'editorial
      Analysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling ...

    • Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2010)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit ...

    • Cross-talk extraction from mask layout 

      Sicard, E.; Demonchaux, T.; Noullet, J.L.; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 1993)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      The principles of an automated cross-talk extractor from the mask-level description of a CMOS integrated circuit are detailed. The physical extraction principles, the techniques for parasitic coupling evaluation and modeling, ...