Exploració per tema "Integrated circuit layout"

Ara es mostren els items 1-3 de 3

    • Lithography aware regular cell design based on a predictive technology model 

      Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja (2010)
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      Accés obert
      As semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated ...

    • Logic synthesis for manufacturability considering regularity and lithography printability 

      Machado, Lucas; Dal Bem, Vinicius; Moll Echeto, Francisco de Borja; Gómez Fernández, Sergio; Ribas, Renato P.; Reis, André Inácio (IEEE Computer Society Publications, 2013)
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      Accés restringit per política de l'editorial
      This paper presents a novel yield model for integrated circuits manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the printability of IC layouts, ...

    • VCTA: A Via-Configurable Transistor Array regular fabric 

      Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2010)
      Text en actes de congrés
      Accés obert
      Layout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper we focus on a scenario where layout regularity ...