• An empirical evaluation of High-Level Synthesis languages and tools for database acceleration 

      Arcas Abella, Oriol; Ndu, Geoffrey; Sönmez, Nehir; Ghasempour, Mohsen; Armejach, Adrià; Navaridas, Javier; Song, Wei; Mawer, John; Cristal Kestelman, Adrián; Lujan, Mikel (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Text en actes de congrés
      Accés obert
      High Level Synthesis (HLS) languages and tools are emerging as the most promising technique to make FPGAs more accessible to software developers. Nevertheless, picking the most suitable HLS for a certain class of algorithms ...
    • FPGA framework improvements for HPC applications 

      Filgueras Izquierdo, Antonio; Vidal, Miquel; Jiménez González, Daniel; Álvarez Martínez, Carlos; Martorell Bofill, Xavier (Institute of Electrical and Electronics Engineers (IEEE), 2023)
      Text en actes de congrés
      Accés obert
      In modern FPGA devices, place and route has become an increasingly difficult task due to an increase in resources and device complexity. This results in an exponential increase of implementation possibilities. Such a huge ...
    • From high-level languages to dataflow circuits 

      Marset Alsina, Joaquim (Universitat Politècnica de Catalunya, 2019-07)
      Treball Final de Grau
      Accés obert
      La manera tradicional de computar alguna cosa és creant software que es pot executar en la unitat de processament central (CPU) d'un processador. El problema és que una CPU no té la capacitat de còmput suficient per executar ...
    • High-level synthesis techniques for reducing the activity of functional units 

      Musoll Cinca, Enric; Cortadella, Jordi (Association for Computing Machinery (ACM), 1995)
      Text en actes de congrés
      Accés obert
      Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during ...
    • OmpSs@cloudFPGA: An FPGA task-based programming model with message passing 

      Haro Ruiz, Juan Miguel de; Cano, Rubén; Álvarez Martínez, Carlos; Jiménez González, Daniel; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Abel, François; Ringlein, Burkhard; Weiss, Beat (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Text en actes de congrés
      Accés obert
      Nowadays, a new parallel paradigm for energy-efficient heterogeneous hardware infrastructures is required to achieve better performance at a reasonable cost on high-performance computing applications. Under this new paradigm, ...
    • OmpSs@FPGA framework for high performance FPGA computing 

      Haro Ruiz, Juan Miguel de; Bosch Pons, Jaume; Filgueras Izquierdo, Antonio; Vidal, Miquel; Jiménez González, Daniel; Álvarez Martínez, Carlos; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José (Institute of Electrical and Electronics Engineers (IEEE), 2021-12-01)
      Article
      Accés obert
      This paper presents the new features of the OmpSs@FPGA framework. OmpSs is a data-flow programming model that supports task nesting and dependencies to target asynchronous parallelism and heterogeneity. OmpSs@FPGA is the ...
    • RTL synthesis: From logic synthesis to automatic pipelining 

      Cortadella, Jordi; Galcerán Oms, Marc; Kishinevsky, Mike; Sapatnekar, Sachin S. (2015-11-01)
      Article
      Accés obert
      Design automation has been one of the main propellers of the semiconductor industry with logic synthesis being one of the core technologies in this field. This article reviews the evolution of logic synthesis until the ...
    • Slow-envelope shaping function FPGA implementation for 5G NR envelope tracking PA 

      Li, Wantao; Bartzoudis, Nikolaos; Rubio Fernández, José; López Bueno, David; Montoro López, Gabriel; Gilabert Pinal, Pere Lluís (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Comunicació de congrés
      Accés restringit per política de l'editorial
      This paper focuses on the FPGA implementation of a slew-rate reduction (SR) shaping function for envelope tracking (ET) power amplifiers (PAs). The SR envelope has been proved effective to trade-off power efficiency and ...