Exploració per tema "High-level synthesis"
Ara es mostren els items 1-8 de 8
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An empirical evaluation of High-Level Synthesis languages and tools for database acceleration
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés obertHigh Level Synthesis (HLS) languages and tools are emerging as the most promising technique to make FPGAs more accessible to software developers. Nevertheless, picking the most suitable HLS for a certain class of algorithms ... -
FPGA framework improvements for HPC applications
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertIn modern FPGA devices, place and route has become an increasingly difficult task due to an increase in resources and device complexity. This results in an exponential increase of implementation possibilities. Such a huge ... -
From high-level languages to dataflow circuits
(Universitat Politècnica de Catalunya, 2019-07)
Treball Final de Grau
Accés obertLa manera tradicional de computar alguna cosa és creant software que es pot executar en la unitat de processament central (CPU) d'un processador. El problema és que una CPU no té la capacitat de còmput suficient per executar ... -
High-level synthesis techniques for reducing the activity of functional units
(Association for Computing Machinery (ACM), 1995)
Text en actes de congrés
Accés obertDecisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during ... -
OmpSs@cloudFPGA: An FPGA task-based programming model with message passing
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertNowadays, a new parallel paradigm for energy-efficient heterogeneous hardware infrastructures is required to achieve better performance at a reasonable cost on high-performance computing applications. Under this new paradigm, ... -
OmpSs@FPGA framework for high performance FPGA computing
(Institute of Electrical and Electronics Engineers (IEEE), 2021-12-01)
Article
Accés obertThis paper presents the new features of the OmpSs@FPGA framework. OmpSs is a data-flow programming model that supports task nesting and dependencies to target asynchronous parallelism and heterogeneity. OmpSs@FPGA is the ... -
RTL synthesis: From logic synthesis to automatic pipelining
(2015-11-01)
Article
Accés obertDesign automation has been one of the main propellers of the semiconductor industry with logic synthesis being one of the core technologies in this field. This article reviews the evolution of logic synthesis until the ... -
Slow-envelope shaping function FPGA implementation for 5G NR envelope tracking PA
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Comunicació de congrés
Accés restringit per política de l'editorialThis paper focuses on the FPGA implementation of a slew-rate reduction (SR) shaping function for envelope tracking (ET) power amplifiers (PAs). The SR envelope has been proved effective to trade-off power efficiency and ...