Exploració per tema "Hardware -- Reliability"

Ara es mostren els items 1-4 de 4

    • Cross-layer system reliability assessment framework for hardware faults 

      Vallero, Alessandro; Savino, Alessandro; Politano, Gianfranco; Di Carlo, Stefano; Chatzidimitriou, Athanansios; Tselonis, Sotiris; Kaliorakis, Manolis; Gizipoulos, Dimitris; Riera Villanueva, Marc; Canal Corretger, Ramon; González Colás, Antonio María; Kooli, Maha; Bosio, Alberto; Di Natale, Giorgio (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Text en actes de congrés
      Accés obert
      System reliability estimation during early design phases facilitates informed decisions for the integration of effective protection mechanisms against different classes of hardware faults. When not all system abstraction ...

    • DRAM errors in the field: a statistical approach 

      Živanovič, Darko; Esmaili Dokht, Pouya; Moré, Sergi; Bartolomé, Javier; Carpenter, Paul Matthew; Radojković, Petar; Ayguadé Parra, Eduard (Association for Computing Machinery (ACM), 2019)
      Text en actes de congrés
      Accés obert
      This paper summarizes our two-year study of corrected and uncor-rected errors on the MareNostrum 3 supercomputer, covering 2000 billion MB-hours of DRAM in the field. The study analyzes 4.5 million corrected and 71 uncorrected ...

    • RVC: A mechanism for time-analyzable real-time processors with faulty caches 

      Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Sazeides, Yanos; Valero Cortés, Mateo (2011)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Geometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM arrays such as caches. Faulty bits can be tolerated from the average performance perspective, but make critical realtime ...

    • The RECIPE approach to challenges in deeply heterogeneous high performance systems 

      Agosta, Giovanni; Fornaciari, William; Atienza, David; Canal Corretger, Ramon; Cilardo, Alessandro; Flich Cardo, José; Hernández Luz, Carles; Kulczewski, Michal; Massari, Giuseppe; Tornero Gavilá, Rafael; Zapater Sancho, Marina (2020-09)
      Article
      Accés obert
      RECIPE (REliable power and time-ConstraInts-aware Predictive management of heterogeneous Exascale systems) is a recently started project funded within the H2020 FETHPC programme, which is expressly targeted at exploring ...