Exploració per tema "Design space exploration"
Ara es mostren els items 1-8 de 8
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A hierarchical mathematical model for automatic pipelining and allocation using elastic systems
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertThe advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical ... -
On the area and energy scalability of wireless network-on-chip: a model-based benchmarked design space exploration
(2014-07-02)
Article
Accés obertNetworks-on-Chip (NoCs) are emerging as the way to interconnect the processing cores and the memory within a chip multiprocessor. As recent years have seen a significant increase in the number of cores per chip, it is ... -
Performance analysis and optimization opportunities for NVIDIA automotive GPUs
(Elsevier, 2021-06)
Article
Accés obertAdvanced Driver Assistance Systems (ADAS) and Autonomous Driving (AD) bring unprecedented performance requirements for automotive systems. Graphic Processing Unit (GPU) based platforms have been deployed with the aim of ... -
Performance analysis of a hardware accelerator of dependence management for taskbased dataflow programming models
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertAlong with the popularity of multicore and manycore, task-based dataflow programming models obtain great attention for being able to extract high parallelism from applications without exposing the complexity to programmers. ... -
Physical vs. physically-aware estimation flow: case study of design space exploration of adders
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialSelecting an appropriate estimation method for a given technology and design is of crucial interest as the estimations guide future project and design decisions. The accuracy of the estimations of area, timing, and power ... -
Scalability of Broadcast Performance in Wireless Network-on-Chip
(IEEE, 2016-12-01)
Article
Accés obertNetworks-on-Chip (NoCs) are currently the paradigm of choice to interconnect the cores of a chip multiprocessor. However, conventional NoCs may not suffice to fulfill the on-chip communication requirements of processors ... -
Scaling of multi-core quantum architectures: a communications-aware structured gap analysis
(Association for Computing Machinery (ACM), 2021)
Text en actes de congrés
Accés obertIn the quest of large-scale quantum computers, multi-core distributed architectures are considered a compelling alternative to be explored. A crucial aspect in such approach is the stringent demand on communication among ... -
Towards reconfigurable accelerators in HPC: Designing a multipurpose eFPGA tile for heterogeneous SoCs
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertThe goal of modern high performance computing platforms is to combine low power consumption and high throughput. Within the European Processor Initiative (EPI), such an SoC platform to meet the novel exascale requirements ...
