Exploració per tema "Delay lines"

Ara es mostren els items 1-4 de 4

    • Diseño y fabricación de líneas de retardo en LTCC 

      Benet Colom, Pablo (Universitat Politècnica de Catalunya, 2015-10-28)
      Projecte Final de Màster Oficial
      Accés obert
      Realitzat a/amb:   Francisco Albero
      In this master's Thesis, a new structure of differential delay line in LTCC was designed, exploiting the benefits that offer this technology for telecommunications and the stacking capability of multiple layers, which let ...

    • Ring oscillator clocks and margins 

      Cortadella, Jordi; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Text en actes de congrés
      Accés obert
      How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA ...

    • Synthesis of all-digital delay lines 

      Moreno Vega, Alberto; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2017)
      Text en actes de congrés
      Accés obert
      The synthesis of delay lines (DLs) is a core task during the generation of matched delays, ring oscillator clocks or delay monitors. The main figure of merit of a DL is the fidelity to track variability. Unfortunately, ...

    • VCTA: A Via-Configurable Transistor Array regular fabric 

      Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2010)
      Text en actes de congrés
      Accés obert
      Layout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper we focus on a scenario where layout regularity ...