Exploració per tema "DRAM"
Ara es mostren els items 1-15 de 15
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Another trip to the wall: how much will stacked DRAM benefit HPC?
(Association for Computing Machinery (ACM), 2015)
Text en actes de congrés
Accés restringit per política de l'editorialFirst defined two decades ago, the memory wall remains a fundamental limitation to system performance. Recent innovations in 3D-stacking technology enable DRAM devices with much higher bandwidths than traditional DIMMs. ... -
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes
(2013)
Text en actes de congrés
Accés restringit per política de l'editorialLow-power modes in modern microprocessors rely on low frequencies and low voltages to reduce the energy budget. Nevertheless, manufacturing induced parameter variations can make SRAM cells unreliable producing hard errors ... -
Detailed tuning and validation of hardware simulators through microbenchmarks
(Barcelona Supercomputing Center, 2018-04-24)
Text en actes de congrés
Accés obert -
Evaluating the impact of future memory technologies in the design of multicore processors
(Universitat Politècnica de Catalunya, 2017-01)
Treball Final de Grau
Accés obert"It’s the Memory, Stupid!" In 1996, Richard Sites, one of the fathers of Computer Architecture and lead designer of the DEC alpha, wrote a paper [36] with the title above. In that paper he realized that the only important ... -
Impact of finfet and III-V/Ge technology on logic and memory cell behavior
(2013-11-20)
Article
Accés restringit per política de l'editorialIn this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios ... -
Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm
(2012)
Text en actes de congrés
Accés obert3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant ... -
Modem gain-cell memories in advanced technologies
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertWith the advent of the slowdown in DRAM capacitor scaling [1] and the increased reliability problems of traditional 6T SRAM memories [2], industry and academia have looked for alternative memory cells. Among those, gain- ... -
Optimization of FinFET-based gain cells for low power sub-vt embedded drams
(2018-06-01)
Article
Accés obertSub-threshold circuits (sub-V T) are a promising alternative in the implementation of low power electronics. The implementation of gain-cell embedded DRAMs (eDRAMs) based on FinFET devices requires a careful design to ... -
PMSS: a programmable memory system and scheduler for complex memory patterns
(2014-10)
Article
Accés restringit per política de l'editorialHPC industry demands more computing units on FPGAs, to enhance the performance by using task/data parallelism. FPGAs can provide its ultimate performance on certain kernels by customizing the hardware for the applications. ... -
PROFET: modeling system performance and energy without simulating the CPU
(2019-06)
Article
Accés obertThe approaching end of DRAM scaling and expansion of emerging memory technologies is motivating a lot of research in future memory systems. Novel memory systems are typically explored by hardware simulators that are slow ... -
Runtime-guided ECC protection using online estimation of memory vulnerability
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertDiminishing reliability of semiconductor technologies and decreasing power budgets per component hinder designing next-generation high performance computing (HPC) systems. Both constraints strongly impact memory subsystems, ... -
StaticHMEM: static object placement methodology for heterogeneous memory systems in HPC
(Universitat Politècnica de Catalunya, 2023-06-26)
Projecte Final de Màster Oficial
Accés obertByte-addressable persistent memory (PMEM) provides memory capacities similar to storage devices,this makes them ideal combination with DRAM as memory extension.Users can either manage the allocation using software or using ... -
Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm
(2014-10-01)
Article
Accés obert3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm ... -
Technological layer
(The Institution of Engineering and Technology, 2020-10)
Capítol de llibre
Accés restringit per política de l'editorialThis chapter describes the fundamental characteristics of Complementary Metal-Oxide-Semiconductor (CMOS) technology, and how it can be assessed for system reliability studies. After some definitions, the dominating ... -
Variability impact on on-chip memory data paths
(2014)
Comunicació de congrés
Accés obertProcess variations have a large impact on device and circuit reliability and performance. Few studies are focused on their impact on more complex systems, as for example their influence in a data path. In our study, the ...
