Exploració per tema "Clocks"

Ara es mostren els items 1-20 de 32

    • A case study for the verification of complex timed circuits: IPCMOS 

      Peña Basurto, Marco Antonio; Cortadella, Jordi; Pastor Llorens, Enric; Smirnov, Alexandre (Institute of Electrical and Electronics Engineers (IEEE), 2002)
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      The verification of a n-stage pulse-driven IPCMOS pipeline, for any n>0, is presented. The complexity of the system is 32n transistors and delay information is provided at the level of transistor The correctness of the ...

    • A multi-radix approach to asynchronous division 

      Cornetta, Gianluca; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2001)
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      The speed of high-radix digit-recurrence dividers is mainly determined by the hardware complexity of the quotient-digit selection function. In this paper we present a scheme that combines the area efficiency of bundled ...

    • A structural encoding technique for the synthesis of asynchronous circuits 

      Carmona Vargas, Josep; Cortadella, Jordi; Pastor Llorens, Enric (Institute of Electrical and Electronics Engineers (IEEE), 2001)
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      This paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is ...

    • Accurate and automatic NOAA-AVHRR image navigation using a global contour matching approach 

      Eugenio, F; Marqués Acosta, Fernando; Gómez, L; Suarez, E; Rovaris, E (2000)
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      The problem of precise and automatic AVHRR image navigation is tractable in theory, but has proved to be somewhat difficult in practice. The authors' work has been motivated by the need for a fully automatic and operational ...

    • All-digital simple clock synthesis through a glitch-free variable-length ring oscillator 

      Pérez Puigdemont, Jordi; Moll Echeto, Francisco de Borja; Calomarde Palomino, Antonio (2014-02-01)
      Article
      Accés restringit per política de l'editorial
      This brief presents a simple all-digital variable-length ring oscillator (VLRO) design that is capable of synchronously changing the output frequency while keeping a signal free of glitches or spurious oscillations at the ...

    • An Extended study on an interference-insensitive switched capacitor CDC 

      Areekath, Lakshmi; Reverter Cubarsí, Ferran; George, Boby (2019-09-15)
      Article
      Accés restringit per política de l'editorial
      A new Switched Capacitor (SC) Capacitance-to-Digital Converter (CDC) is presented in this paper. Its output exhibits a high-level of insensitivity to interference, by virtue of the conversion mechanism itself. The proposed ...

    • Architecture and performance of the KM3NeT front-end firmware 

      Aiello, S; Albert, Arnauld; Alves Garre, Sergio; Zineb, Aly; Ameli, Fabrizio; André, Michel; Androulakis, Giorgos; Anghinolfi, Marco; Anguita, M.; Anton, Gisela (International Society for Photo-Optical Instrumentation Engineers (SPIE), 2021-01-01)
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      Accés obert
      The KM3NeT infrastructure consists of two deep-sea neutrino telescopes being deployed in the Mediterranean Sea. The telescopes will detect extraterrestrial and atmospheric neutrinos by means of the incident photons induced ...

    • Automatic microarchitectural pipelining 

      Galcerán Oms, Marc; Cortadella, Jordi; Bufistov, Dmitry; Kishinevsky, Michael (Institute of Electrical and Electronics Engineers (IEEE), 2010)
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      This paper presents a method for automatic microarchitectural pipelining of systems with loops. The original specification is pipelined by performing provably-correct transformations including conversion to a synchronous ...

    • Behavioral transformations to increase the noise immunity of asynchronous specifications 

      Taubin, Alexander; Kondratyev, Alex; Cortadella, Jordi; Lavagno, Luciano (Institute of Electrical and Electronics Engineers (IEEE), 1999)
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      Noise immunity is becoming one of the most important design parameters for deep-sub-micron (DSM) technologies. Asynchronous circuits seem to be a good candidate to alleviate the problems originated by simultaneous switching ...

    • CAD directions for high performance asynchronous circuits 

      Stevens, Kenneth S.; Rotem, Shai; Burns, Steven M.; Cortadella, Jordi; Ginosar, Ran; Kishinevsky, Michael; Roncken, Marly (Association for Computing Machinery (ACM), 1999)
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      This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using relative timing. This methodology was developed for a prototype iA32 ...

    • Coping with the variability of combinational logic delays 

      Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Sotiriou, Christos P. (Institute of Electrical and Electronics Engineers (IEEE), 2004)
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      This paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on dual-rail encoding, and guarantees low timing overhead ...

    • Design and implementation of a 5/spl times/5 trits multiplier in a quasi-adiabatic ternary CMOS logic 

      Mateo Peña, Diego; Rubio Sola, Jose Antonio (1998-07)
      Article
      Accés obert
      Adiabatic switching is a technique to design low-power digital IC's. Fully adiabatic logics have expensive silicon area requirements. To solve this drawback, a quasi-adiabatic ternary logic is proposed. Its basis is ...

    • Design and implementation of a sliding-mode controller for digital low-dropout/linear regulators 

      Baheri, Javad; Saberkari, Alireza; Khorgami, Omid; Alarcón Cot, Eduardo José (2018-03-20)
      Article
      Accés obert
      This paper presents an approach to utilize of sliding-mode (SM) controller in digital low-dropout/linear regulators. Various design aspects, including the extraction of the regulator state-space model and sliding coefficients ...

    • Empowering a helper cluster through data-width aware instruction selection policies 

      Unsal, Osman Sabri; Ergin, Oguz; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society, 2006)
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      Narrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. On the other hand, clustering mechanisms enable cost- and performance-effective scaling of processor ...

    • Freezing Time: a new approach for emulating fast storage devices using VM 

      Bona, Luis C.E.; Elias, Alessandro; Ziviani, Andre P.; Cortés, Toni; Nou Castell, Ramon; Alves, Marco A.Z. (Institute of Electrical and Electronics Engineers (IEEE), 2018)
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      Recently we are seeing a considerable effort from both academy and industry in proposing new technologies for storage devices. Often these devices are not readily available for evaluation and methods to allow performing ...

    • From synchronous to asynchronous: an automatic approach 

      Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Lwin, Kelvin; Sotiriou, Christos P. (Institute of Electrical and Electronics Engineers (IEEE), 2004)
      Text en actes de congrés
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      This paper presents a methodology to derive asynchronous circuits from optimized synchronous circuits by replacing the clock distribution tree by a handshaking network. A case study shows the applicability of the method ...

    • Frontend frequency-voltage adaptation for optimal energy-delay/sup 2/ 

      Grigorios, Magklis; González González, José; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2004)
      Text en actes de congrés
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      In this paper, we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines the benefits of both clustering and globally asynchronous locally synchronous (GALS) designs. We also present a mechanism ...

    • Handshake protocols for de-synchronization 

      Blunno, Ivan; Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Lwin, Kelvin; Sotiriou, Christos P. (Institute of Electrical and Electronics Engineers (IEEE), 2004)
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      De-synchronization appears as a new paradigm to automate the design of asynchronous circuits from synchronous netlists. This paper studies different protocols for de-synchronization and formally proves their correctness. ...

    • High-Performance low-vcc in-order core 

      Abella Ferrer, Jaume; Chaparro, Pedro; Vera Rivera, Francisco Javier; Carretero Casado, Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2010)
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      Power density grows in new technology nodes, thus requiring Vcc to scale especially in mobile platforms where energy is critical. This paper presents a novel approach to decrease Vcc while keeping operating frequency high. ...

    • Impact of parameter variations on circuits and microarchitecture 

      Unsal, Osman Sabri; Tschanz, James W.; Bowman, Keith; De, Vivek; Vera Rivera, Francisco Javier; González Colás, Antonio María; Ergin, Oguz (2006-12)
      Article
      Accés obert
      Parameter variations, which are increasing along with advances in process technologies, affect both timing and power. Variability must be considered at both the circuit and microarchitectural design levels to keep pace ...