Exploració per tema "Circuits integrats -- CMOS"

Ara es mostren els items 1-4 de 4

    • Measuring the tolerance of self-adaptive clocks to supply voltage noise 

      Pérez Puigdemont, Jordi; Moll Echeto, Francisco de Borja; Cortadella, Jordi (2011)
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      Accés obert
      Simultaneous switching noise has become an important issue due to its signal integrity and timing implications. Therefore a lot of time and resources are spent during the PDN design to minimize the supply voltage variation. ...

    • Monitor strategies for variability reduction considering correlation between power and timing variability 

      Mauricio Ferré, Juan; Moll Echeto, Francisco de Borja; Altet Sanahujes, Josep (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
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      Accés restringit per política de l'editorial
      As CMOS technology scales, Process, Voltage and Temperature (PVT) variations have an increasing impact on, performance and power consumption of the electronic devices. Variability causes an undesirable dispersion of ...

    • Power supply noise and logic error probability 

      Andrade Miceli, Dennis Michael; Martorell Cid, Ferran; Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2007-08)
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      Voltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing ...

    • Voltage fluctuations in IC power supply distribution 

      Andrade Miceli, Dennis Michael; Martorell Cid, Ferran; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2007-11)
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      Accés obert
      The supply voltage decrease and power consumption increase of modern ICs made the requirements for low voltage fluctuation caused by packaging and on-chip parasitic impedances more difficult to achieve. Most of the research ...