Exploració per tema "Circuits asíncrons"
Ara es mostren els items 1-20 de 59
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A multi-radix approach to asynchronous division
(Institute of Electrical and Electronics Engineers (IEEE), 2001)
Text en actes de congrés
Accés obertThe speed of high-radix digit-recurrence dividers is mainly determined by the hardware complexity of the quotient-digit selection function. In this paper we present a scheme that combines the area efficiency of bundled ... -
A region-based theory for state assignment in speed-independent circuits
(1997-08)
Article
Accés obertState assignment problems still need satisfactory solutions to make asynchronous circuit synthesis more practical. A well-known example of such a problem is that of complete state coding (CSC), which happens when a pair ... -
A structural encoding technique for the synthesis of asynchronous circuits
(Institute of Electrical and Electronics Engineers (IEEE), 2001)
Text en actes de congrés
Accés obertThis paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is ... -
Asynchronous multipliers with variable-delay counters
(Institute of Electrical and Electronics Engineers (IEEE), 2001)
Text en actes de congrés
Accés obertAlthough multiplication is an intensely studied arithmetic operation and many fast algorithms and implementations are available, it still represents one of the major bottlenecks of many digital systems that require intensive ... -
Automatic generation of synchronous test patterns for asynchronous circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Text en actes de congrés
Accés obertThis paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exercised by applying synchronous test vectors, ... -
Automatic synthesis and optimization of partially specified asynchronous systems
(Association for Computing Machinery (ACM), 1999)
Text en actes de congrés
Accés obertA method for automating the synthesis of asynchronous control circuits from high level (CSP-like) and/or partial STG (involving only functionally critical events) specifications is presented. The method solves two key ... -
Behavioral transformations to increase the noise immunity of asynchronous specifications
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertNoise immunity is becoming one of the most important design parameters for deep-sub-micron (DSM) technologies. Asynchronous circuits seem to be a good candidate to alleviate the problems originated by simultaneous switching ... -
Bridging modularity and optimality: delay-insensitive interfacing in asynchronous circuits synthesis
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertTwo trends are of major concern for digital circuit designers: the relative increase of interconnect delays with respect to gate delays and the demand for design reuse. Both pose difficult problems to synchronous design ... -
CAD directions for high performance asynchronous circuits
(Association for Computing Machinery (ACM), 1999)
Text en actes de congrés
Accés obertThis paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using relative timing. This methodology was developed for a prototype iA32 ... -
Checking signal transition graph implementability by symbolic bdd traversal
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Text en actes de congrés
Accés obertThis paper defines conditions for a Signal Transition Graph to be implemented by an asynchronous circuit. A hierarchy of the implementability classes is presented. Our main concern is the implementability of the specification ... -
Clustering for the optimisation of asynchronous controllers
(Universitat Politècnica de Catalunya, 2008-06-25)
Projecte Final de Màster Oficial
Accés obert -
Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Text en actes de congrés
Accés obertThis paper presents a new methodology to automatically synthesize asynchronous circuits from descriptions based on process algebra. Traditionally, syntax-directed techniques have been used to generate a netlist of basic ... -
Complete state encoding based on the theory of regions
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Text en actes de congrés
Accés obertSynthesis of asynchronous circuits from Signal Transition Graphs (STGs) and/or State Graphs (SGs) involves solving state coding problems. A well-known example of such problems is that of Complete State Coding (CSC), which ... -
Concurrency primitives in Haskell
(Universitat Politècnica de Catalunya, 2016-06-27)
Treball Final de Grau
Accés obert
Realitzat a/amb: University of Newcastle upon Tyne -
Coping with the variability of combinational logic delays
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertThis paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on dual-rail encoding, and guarantees low timing overhead ... -
Decomposition and technology mapping of speed-independent circuits using Boolean relations
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Text en actes de congrés
Accés obertPresents a new technique for the decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in ... -
Decomposition and technology mapping of speed-independent circuits using Boolean relations
(1999-09)
Article
Accés obertThis paper presents a new technique for decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available ... -
Design of a column decoder for a binary vision sensor implementing run length encoding
(Universitat Politècnica de Catalunya / Università degli Studi di Trento, 2014)
Treball Final de Grau
Accés obert
Realitzat a/amb: Università degli studi di TrentoThis work describes the architecture of an asynchronous column decoder for a CMOS binary vision sensor. The decoder compresses and code data, at row-level, before delivering off-chip. The operation is completely asynchronous ... -
Designing asynchronous circuits from behavioural specifications with internal conflicts
(Institute of Electrical and Electronics Engineers (IEEE), 1994)
Text en actes de congrés
Accés obertThe paper presents a systematic method for synthesizing asynchronous circuits from event-based specifications with conflicts on output signals. It describes a set of semantic-preserving transformations performed at the ... -
Desynchronization: Synthesis of asynchronous circuits from synchronous specifications
(2006-10)
Article
Accés obertAsynchronous implementation techniques, which measure logic delays at runtime and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst case delays at design ...