Exploració per tema "Chip multiprocessor"
Ara es mostren els items 1-6 de 6
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Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems
(2015-07-01)
Article
Accés obertManycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the network-on-chip and the coherence protocol, improves performance and power meanwhile ... -
Near-optimal replacement policies for shared caches in multicore processors
(2021-10)
Article
Accés obertAn optimal replacement policy that minimizes the miss rate in a private cache was proposed several decades ago. It requires knowing the future access sequence the cache will receive. There is no equivalent for shared caches ... -
Physical-aware system-level design for tiled hierarchical chip multiprocessors
(ACM Press. Association for Computing Machinery, 2013)
Text en actes de congrés
Accés obertTiled hierarchical architectures for Chip Multiprocessors (CMPs) represent a rapid way of building scalable and power-e fficient many-core computing systems. At the early stages of the design of a CMP, physical parameters ... -
Power/performance/thermal design-space exploration for multicore architectures
(2008-05)
Article
Accés obertMulticore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern applications, ILP diminishing returns, better ... -
ReD: A reuse detector for content selection in exclusive shared last-level caches
(Elsevier, 2019-03)
Article
Accés obertThe reference stream reaching a chip multiprocessor Shared Last-Level Cache (SLLC) shows poor temporal locality, making conventional cache management policies inefficient. Few proposals address this problem for exclusive ... -
Using coherence information and decay techniques to optimize L2 cache leakage in CMPs
(IEEE Computer Society, 2009)
Text en actes de congrés
Accés obertThis paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this case, coherence must be enforced in all ...