Ara es mostren els items 1-10 de 10

    • A complexity-effective simultaneous multithreading architecture 

      Acosta Ojeda, Carmelo Alexis; Falcón Samper, Ayose Jesús; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2005)
      Text en actes de congrés
      Accés obert
      Different applications may exhibit radically different behaviors and thus have very different requirements in terms of hardware support. In simultaneous multithreading (SMT) architectures, the hardware is shared among ...
    • An analyzable memory controller for hard real-time CMPs 

      Paolieri, Marco; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (2010-02-05)
      Article
      Accés obert
      Multicore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences ...
    • Characterizing political statements using deep learning techniques 

      Albiach Caro, Sergi (Universitat Politècnica de Catalunya, 2023-10-19)
      Projecte Final de Màster Oficial
      Accés obert
      Political science is interested in understanding where political parties are positioned on several socioeconomic scales and how these evolve through time. A huge number of resources, mostly human, are spent on codifying ...
    • Exploring coordinated software and hardware support for hardware resource allocation 

      Figueiredo Boneti, Carlos Santieri de (Universitat Politècnica de Catalunya, 2009-09-04)
      Tesi
      Accés obert
      Multithreaded processors are now common in the industry as they offer high performance at a low cost. Traditionally, in such processors, the assignation of hardware resources between the multiple threads is done implicitly, ...
    • Physical planning for the architectural exploration of large-scale chip multiprocessors 

      San Pedro Martín, Javier de; Nikitin, Nikita; Cortadella, Jordi; Petit Silvestre, Jordi (2013)
      Comunicació de congrés
      Accés restringit per política de l'editorial
      This paper presents an integrated flow for architectural exploration and physical planning of large-scale hierarchical tiled CMPs. Classical floorplanning and wire planning techniques have been adapted to incorporate layout ...
    • Runtime estimation of performance–power in CMPs under QoS constraints 

      Nishtala, Rajiv; Martorell Bofill, Xavier; Carpenter, Paul Matthew (Barcelona Supercomputing Center, 2015-05-05)
      Text en actes de congrés
      Accés obert
      One of the main challenges in data center systems is operating under certain Quality of Service (QoS) while minimizing power consumption. Increasingly, data centers are exploring and adopting heterogeneous server architectures ...
    • Simulación multiescala de arquitecturas paralelas 

      Martinez Vera, Juan Francisco (Universitat Politècnica de Catalunya, 2016-01-26)
      Treball Final de Grau
      Accés obert
      Se han analizado y desarrollado diferentes metodologías que permiten la simulación conjunta entre Dimemas y Sniper, consiguiendo modelar un cluster siguiendo la propuesta de simulación multiescala. La infraestructura ...
    • Solving multiprocessor drawbacks with kilo-instruction processors 

      Vallejo, Enrique; Galluzzi, Marco; Cristal Kestelman, Adrián; Vallejo, Fernando; Beivide Palacio, Ramon; Stenström, Per; Smith, James E.; Valero Cortés, Mateo (2005)
      Report de recerca
      Accés obert
      Nowadays, a good multiprocessor system design has to deal with many drawbacks in order to achieve a good tradeoff between complexity and performance. For example, while solving problems like coherence and consistency is ...
    • Trace compression mechanisms for the efficient simulation of CMP 

      Rivas Barragan, Daniel (Universitat Politècnica de Catalunya, 2014-07-09)
      Projecte Final de Màster Oficial
      Accés obert
      In this project we present, first, a new mechanism to find patterns in memory accesses and then compress them achieving compress ratios higher than 200x without compromising decompression performance. We also present a new ...
    • Using coherence information and decay techniques to optimize L2 cache leakage in CMPs 

      Monchiero, Matteo; Canal Corretger, Ramon; González Colás, Antonio María (IEEE Computer Society, 2009)
      Text en actes de congrés
      Accés obert
      This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this case, coherence must be enforced in all ...