Exploració per autor "Vallejo, Fernando"

Ara es mostren els items 7-9 de 9

    • Light NUCA: a proposal for bridging the inter-cache latency gap 

      Suárez, Dario; Monreal Arnal, Teresa; Vallejo, Fernando; Beivide Palacio, Julio Ramón; Viñals Yufera, Víctor (IEEE Computer Society, 2009)
      Comunicació de congrés
      Accés obert
      To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between them and fast L1 caches (inter-cache latency gap). ...

    • Solving multiprocessor drawbacks with kilo-instruction processors 

      Vallejo, Enrique; Galluzzi, Marco; Cristal Kestelman, Adrián; Vallejo, Fernando; Beivide Palacio, Ramon; Stenström, Per; Smith, James E.; Valero Cortés, Mateo (2005)
      Report de recerca
      Accés obert
      Nowadays, a good multiprocessor system design has to deal with many drawbacks in order to achieve a good tradeoff between complexity and performance. For example, while solving problems like coherence and consistency is ...

    • Towards fair, scalable, locking 

      Vallejo, Enrique; Sanyal, Sutirtha; Harris, Tim; Vallejo, Fernando; Beivide Palacio, Ramon; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2008)
      Text en actes de congrés
      Accés obert
      Without care, Hardware Transactional Memory presents several performance pathologies that can degrade its performance. Among them, writers of commonly read variables can suffer from starvation. Though different solutions ...