Exploració per autor "Vallejo, Enrique"
Ara es mostren els items 18-23 de 23
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Solving multiprocessor drawbacks with kilo-instruction processors
Vallejo, Enrique; Galluzzi, Marco; Cristal Kestelman, Adrián; Vallejo, Fernando; Beivide Palacio, Ramon; Stenström, Per; Smith, James E.; Valero Cortés, Mateo (2005)
Report de recerca
Accés obertNowadays, a good multiprocessor system design has to deal with many drawbacks in order to achieve a good tradeoff between complexity and performance. For example, while solving problems like coherence and consistency is ... -
Task mapping in rectangular twisted tori
Camarero Coterillo, Cristobal; Vallejo, Enrique; Martínez Fernández, Maria del Carmen; Moretó Planas, Miquel; Beivide Palacio, Julio Ramón (Association for Computing Machinery (ACM), 2013)
Text en actes de congrés
Accés obertTwisted torus topologies have been proposed as an alternative to toroidal rectangular networks, improving distance parameters and providing network symmetry. However, twisting is apparently less amenable to task mapping ... -
The Mont-Blanc prototype: an alternative approach for high-performance computing systems
Rajovic, Nikola; Ramírez Bellido, Alejandro; Rico, Alejandro; Mantovani, Filippo; Ruiz, Daniel; Villarubi, Oriol; Gómez, Constantino; Backes, Luna; Nieto, Diego; Servat, Harald; Martorell Bofill, Xavier; Labarta Mancho, Jesús José; Ayguadé Parra, Eduard; Valero Cortés, Mateo; Adeniyi-Jones, Chris; Derradji, Said; Gloaguen, Hervé; Lanucara, Piero; Sanna, Nico; Mehaut, Jean-François; Pouget, Kevin; Videau, Brice; Boyer, Eric; Allalen, Momme; Auweter, Axel; Brayford, David; Tafani, Daniele; Brömmel, Dirk; Halver, René; Meinke, Jan H.; Beivide Palacio, Ramon; Benito, Mariano; Vallejo, Enrique (2016)
Report de recerca
Accés obertHigh-performance computing (HPC) is recognized as one of the pillars for further advance of science, industry, medicine, and education. Current HPC systems are being developed to overcome emerging challenges in order to ... -
The Mont-Blanc prototype: an alternative approach for HPC systems
Rajovic, Nikola; Rico, Alejandro; Mantovani, Filippo; Ruiz, Daniel; Vlarrubi, Josep O.; Gomez, Constantino; Backes, Luna; Nieto, Diego; Servat, Harald; Martorell Bofill, Xavier; Labarta Mancho, Jesús José; Ayguadé Parra, Eduard; Adeniyi-Jones, Chris; Derradji, Said; Gloaguen, Hervé; Lanucara, Piero; Sanna, Nico; Mehaut, Jean-François; Pouget, Kevin; Videau, Brice; Boyer, Eric; Allalen, Momme; Auweter, Axel; Brayford, David; Tafani, Daniele; Weinberg, Volker; Brömmel, Dirk; Halver, René; Meinke, Jan H.; Beivide Palacio, Ramon; Benito, Mariano; Vallejo, Enrique; Valero Cortés, Mateo; Ramirez, Alex (Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertHigh-performance computing (HPC) is recognized as one of the pillars for further progress in science, industry, medicine, and education. Current HPC systems are being developed to overcome emerging architectural challenges ... -
Throughput unfairness in Dragonfly networks under realistic traffic patterns
Fuentes, Pablo; Vallejo, Enrique; Camarero, Cristóbal; Beivide Palacio, Ramon; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés obertDragonfly networks have a two-level hierarchical arrangement of the network routers, and allow for a competitive cost-performance solution in large systems. Non-minimal adaptive routing is employed to fully exploit the ... -
Towards fair, scalable, locking
Vallejo, Enrique; Sanyal, Sutirtha; Harris, Tim; Vallejo, Fernando; Beivide Palacio, Ramon; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2008)
Text en actes de congrés
Accés obertWithout care, Hardware Transactional Memory presents several performance pathologies that can degrade its performance. Among them, writers of commonly read variables can suffer from starvation. Though different solutions ...