Exploració per autor "Renovell, Michel"
Ara es mostren els items 1-6 de 6
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Power-aware voltage tuning for STT-MRAM reliability
Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Di Carlo, Stefano; Renovell, Michel; Prinetto, Paolo; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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Accés restringit per política de l'editorialOne of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low area, low power consumption, and good scaling capability. ... -
Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell
Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Indaco, Marco; Renovell, Michel; Prinetto, Paolo; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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Accés restringit per política de l'editorialThe rapid development of low power, high density, high performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin- Transfer-Torque ... -
Robustness of SRAM to Power Supply Noise during Leakage Power Saving in DVS
Vatajelu, Elena Ioana; Renovell, Michel; Figueras Pàmies, Joan (IEEE Press. Institute of Electrical and Electronics Engineers, 2010)
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SRAM cell stability metric under transient voltage noise
Vatajelu, Elena Ioana; Gómez Pau, Álvaro; Renovell, Michel; Figueras Pàmies, Joan (2013-12-20)
Article
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SRAM stability metric under transient noise
Vatajelu, Elena Ioana; Gómez Pau, Álvaro; Renovell, Michel; Figueras Pàmies, Joan (2012)
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Accés obertventional way to analyze the robustness of an SRAM bit cell is to quantify its immunity to static noise. The static immunity to disturbances like process and mi smatch variations, bulk noises, supply rings variations, ... -
Transient noise failures in SRAM cells: dynamic noise margin metric
Vatajelu, Elena Ioana; Gómez Pau, Álvaro; Renovell, Michel; Figueras Pàmies, Joan (IEEE Computer Society Publications, 2011)
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Accés restringit per política de l'editorialCurrent nanometric IC processes need to assess the robustness of memories under any possible source of disturbance: process and mismatch variations, bulk noises, supply rings variations, temperature changes, aging and ...