Ara es mostren els items 23-42 de 61

    • Fitting processor architectures for measurement-based probabilistic timing analysis 

      Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Vardanega, Tullio; Hernández, Carles; Gianarro, Andrea; Broster, Ian; Cazorla Almeida, Francisco Javier (2016-11-01)
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      The pressing market demand for competitive performance/cost ratios compels Critical Real-Time Embedded Systems industry to employ feature-rich hardware. The ensuing rise in hardware complexity however makes worst-case ...
    • Framework for the Analysis and Configuration of Real-Time OpenMP Applications 

      Carvalho, Tiago; Pinho, Luis Miguel; Samadi, Mohammad; Royuela, Sara; Munera, Adrian; Quiñones, Eduardo (Institute of Electrical and Electronics Engineers (IEEE), 2023)
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      High-performance cyber-physical applications impose several requirements with respect to performance, functional correctness and non-functional aspects. Nowadays, the design of these systems usually follows a model-driven ...
    • Improving branch prediction and predicated execution in out-of-order processors 

      Quiñones, Eduardo; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2007)
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      If-conversion is a compiler technique that reduces the misprediction penalties caused by hard-to-predict branches, transforming control dependencies into data dependencies. Although it is globally beneficial, it has a ...
    • Improving performance guarantees in wormhole mesh NoC designs 

      Panic, Milos; Hernández, Carles; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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      Wormhole-based mesh Networks-on-Chip (wNoC) are deployed in high-performance many-core processors due to their physical scalability and low-cost. Delivering tight and time composable Worst-Case Execution Time (WCET) estimates ...
    • Leveraging register windows to reduce physical registers to the bare minimum 

      Quiñones, Eduardo; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (2010-12)
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      Register window is an architectural technique that reduces memory operations required to save and restore registers across procedure calls. Its effectiveness depends on the size of the register file. Such register requirements ...
    • Measurement-based probabilistic timing analysis for multi-path programs 

      Cucu Grosjean, Liliana; Santinelli, Luca; Houston, Michael; Lo, Code; Vardanega, Tulio; Kosmidis, Leonidas; Abella Ferrer, Jaume; Mezzetti, Enrico; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (2012)
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      The rigorous application of static timing analysis requires a large and costly amount of detail knowledge on the hardware and software components of the system. Probabilistic Timing Analysis has potential for reducing the ...
    • Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study 

      Wartel, Franck; Kosmidis, Leonidas; Lo, Code; Triquet, Benoit; Quiñones, Eduardo; Abella Ferrer, Jaume; Gogonel, Adriana; Baldovin, Andrea; Mezzetti, Enrico; Cucu Grosjean, Liliana; Vardanega, Tulio; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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      Probabilistic Timing Analysis (PTA) in general and its measurement-based variant called MBPTA in particular can mitigate some of the problems that impair current worst-case execution time (WCET) analysis techniques. MBPTA ...
    • Measurement-based timing analysis of the AURIX caches 

      Kosmidis, Leonidas; Compagnin, Davide; Morales, David; Mezzetti, Enrico; Quiñones, Eduardo; Abella Ferrer, Jaume; Vardanega, Tullio; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2016)
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      Cache memories are one of the hardware resources with higher potential to reduce worst-case execution time (WCET) costs for software programs with tight real-time constraints. Yet, the complexity of cache analysis has ...
    • Modeling high-performance wormhole NoCs for critical real-time embedded systems 

      Panic, Milos; Hernández, Carles; Quiñones, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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      Manycore chips are a promising computing platform to cope with the increasing performance needs of critical real-time embedded systems (CRTES). However, manycores adoption by CRTES industry requires understanding task's ...
    • Modelling the confidence of timing analysis for time randomised caches 

      Benedicte Illescas, Pedro; Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Text en actes de congrés
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      Timing is a key non-functional property in embedded real-Time systems (ERTS). ERTS increasingly require higher levels of performance that can only be sensibly provided by deploying high-performance hardware, which however ...
    • Multi-level unified caches for probabilistically time analysable real-time systems 

      Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (IEEEXPLORE, 2013)
      Text en actes de congrés
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      Caches are key resources in high-end processor architectures to increase performance. In fact, most high-performance processors come equipped with a multi-level cache hierarchy. In terms of guaranteed performance, however, ...
    • On the convergence of mainstream and mission-critical markets 

      Girbal, Sylvain; Moretó Planas, Miquel; Grasset, Arnaud; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Yehia, Sami (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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      The computing market has been dominated during the last two decades by the well-known convergence of the highperformance computing market and the mobile market. In this paper we witness a new type of convergence between ...
    • OpenMP static TDG runtime implementation and its usage in heterogeneous computing 

      Yu, Chenle; Royuela Alcázar, Sara; Quiñones, Eduardo (Barcelona Supercomputing Center, 2020-05)
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      OpenMP being the standard to use in shared memory parallel programming, it offers the possibility to parallelize sequential program with accelerators by using target directive. However, CUDA Graph as a new, efficient ...
    • Parcus: Energy-Aware and Robust Parallelization of AUTOSAR Legacy Applications 

      Kehr, Sebastian; Quiñones, Eduardo; Langen, Dominik; Böddeker, Bert; Schäfer, Günter (Institute of Electrical and Electronics Engineers (IEEE), 2017-06-08)
      Comunicació de congrés
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      Embedded multicore processors are an attractive alternative to sophisticated single-core processors for the use in automobile electronic control units (ECUs), due to their expected higher performance and energy efficiency. ...
    • Probabilistic timing analysis on conventional cache designs 

      Kosmidis, Leonidas; Curtsinger, Charlie; Quiñones, Eduardo; Abella Ferrer, Jaume; Berger, Emery D.; Cazorla Almeida, Francisco Javier (2013)
      Text en actes de congrés
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      Probabilistic timing analysis (PTA), a promising alternative to traditional worst-case execution time (WCET) analyses, enables pairing time bounds (named probabilistic WCET or pWCET) with an exceedance probability (e.g., ...
    • Probabilistic timing analysis on time-randomized platforms for the space domain 

      Fernandez, Mikel; Morales, David; Kosmidis, Leonidas; Bardizbanyan, Alen; Broster, Ian; Hernandez, Carles; Quiñones, Eduardo; Abella Ferrer, Jaume; Cazorla, Francisco; Machado, Paulo; Fossati, Luca (Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
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      Timing Verification is a fundamental step in real-time embedded systems, with measurement-based timing analysis (MBTA) being the most common approach used to that end. We present a Space case study on a real platform that ...
    • PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis 

      Cazorla, Francisco J.; Abella Ferrer, Jaume; Andersson, Jan; Vardanega, Tullio; Vatrinet, Francis; Bate, Iain; Broster, Ian; Azkarate-askasua, Mikel; Wartel, Franck; Cucu, Liliana; Cros, Fabrice; Farrall, Glenn; Gogonel, Adriana; Gianarro, Andrea; Triquet, Benoit; Hernandez, Carles; Lo, Code; Maxim, Cristian; Morales, David; Quiñones, Eduardo; Mezzetti, Enrico; Kosmidis, Leonidas; Aguirre, Irune; Fernandez, Mikel; Slijepcevic, Mladen; Conmy, Philippa; Talaboulma, Walid (IEEE, 2016-08-31)
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      The use of increasingly complex hardware and software platforms in response to the ever rising performance demands of modern real-time systems complicates the verification and validation of their timing behaviour, which ...
    • pTNoC: Probabilistically time-analyzable tree-based NoC for mixed-criticality systems 

      Slijepcevic, Mladen; Fernández, Mikel; Hernández, Carles; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Text en actes de congrés
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      The use of networks-on-chip (NoC) in real-time safety-critical multicore systems challenges deriving tight worst-case execution time (WCET) estimates. This is due to the complexities in tightly upper-bounding the contention ...
    • Real-time Issues in the Ada Parallel Model with OpenMP 

      Pinho, Luis Miguel; Royuela Alcázar, Sara; Quiñones, Eduardo (Association for Computing Machinery, 2021)
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      The current proposal for the next revision of the Ada language considers the possibility to map the language parallel features to an underlying OpenMP runtime. As previously presented, and discussed in previous workshops, ...
    • Response-time analysis of DAG tasks supporting heterogeneous computing 

      Serrano Gracia, María Astón; Quiñones, Eduardo (Association for Computing Machinery (ACM), 2018-06-24)
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