• An hybrid eDRAM/SRAM macrocell to implement first-level data caches 

      Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; Lorente, Vicente; Canal Corretger, Ramon; López, Pedro; Duato, José (Association for Computing Machinery (ACM), 2009)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are ...
    • Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes 

      Lorente, Vicente; Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; Canal Corretger, Ramon; López, Pedro; Duato, José (2013)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Low-power modes in modern microprocessors rely on low frequencies and low voltages to reduce the energy budget. Nevertheless, manufacturing induced parameter variations can make SRAM cells unreliable producing hard errors ...