Ara es mostren els items 10-11 de 11

    • Software-controlled priority characterization of POWER5 processor 

      Boneti, Carlos; Cazorla, Francisco; Gioiosa, Roberto; Buyuktosunoglu, Alper; Cher, Chen-Yong; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
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      Due to the limitations of instruction-level parallelism, thread-level parallelism has become a popular way to improve processor performance. One example is the IBM POWER5TM processor, a two-context simultaneous-multithreaded ...
    • Understanding the overhead of the spin-lock loop in CMT architectures 

      Cakarevic, Vladimir; Radojković, Petar; Verdú Mulà, Javier; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Pajuelo González, Manuel Alejandro; Nemirovsky, Mario; Valero Cortés, Mateo (2008)
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      Spin locks are a synchronization mechanisms used to provide mutual exclusion to shared software resources. Spin locks are used over other synchronization mechanisms in several situations, like when the average waiting ...