Exploració per autor "Ergin, Oguz"
Ara es mostren els items 1-11 de 11
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A novel FPGA-based high throughput accelerator for binary search trees
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertThis paper presents a deeply pipelined and massively parallel Binary Search Tree (BST) accelerator for Field Programmable Gate Arrays (FPGAs). Our design relies on the extremely parallel on-chip memory, or Block RAMs (BRAMs) ... -
An experimental study of reduced-voltage operation in modern FPGAs for neural network acceleration
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertWe empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field ... -
Can we trust undervolting in FPGA-based deep learning designs at harsh conditions?
(2022-05)
Article
Accés obertAs more Neural Networks on Field Programmable Gate Arrays (FPGAs) are used in a wider context, the importance of power efficiency increases. However, the focus on power should never compromise application accuracy. One ... -
Compiler directed early register release
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertThis paper presents a novel compiler directed technique to reduce the register pressure and power of the register file by releasing registers early. The compiler identifies registers that mil only be read once and renames ... -
Empowering a helper cluster through data-width aware instruction selection policies
(IEEE Computer Society, 2006)
Text en actes de congrés
Accés obertNarrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. On the other hand, clustering mechanisms enable cost- and performance-effective scaling of processor ... -
Exploiting narrow values for soft error tolerance
(2006-07)
Article
Accés obertSoft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. ... -
Fuse: A technique to anticipate failures due to degradation in ALUs
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Text en actes de congrés
Accés obertThis paper proposes the fuse, a technique to anticipate failures due to degradation in any ALU (arithmetic logic unit), and particularly in an adder. The fuse consists of a replica of the weakest transistor in the adder ... -
Impact of parameter variations on circuits and microarchitecture
(2006-12)
Article
Accés obertParameter variations, which are increasing along with advances in process technologies, affect both timing and power. Variability must be considered at both the circuit and microarchitectural design levels to keep pace ... -
MoRS: An approximate fault modelling framework for reduced-voltage SRAMs
(2022-06)
Article
Accés obertOn-chip memory (usually based on Static RAMs-SRAMs) are crucial components for various computing devices including heterogeneous devices, e.g, GPUs, FPGAs, ASICs to achieve high performance. Modern workloads such as Deep ... -
Reducing soft errors through operand width aware policies
(2009-09)
Article
Accés obertSoft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. ... -
Refueling: Preventing wire degradation due to electromigration
(2008-12)
Article
Accés obertElectromigration is a major source of wire and via failure. Refueling undoes EM for bidirectional wires and power/ground grids-some of a chip's most vulnerable wires. Refueling exploits EM's self-healing effect by balancing ...
