• Efficient bypass in mesh and torus NoCs 

      Pérez, Iván; Vallejo, Enrique; Beivide, Ramón (Elsevier, 2020)
      Article
      Accés obert
      Minimizing latency and power are key goals in the design of NoC routers. Different proposals combine lookahead routing and router bypass to skip the arbitration and buffering, reducing router delay. However, the conditions ...
    • Hybrid transactional memory with pessimistic concurrency control 

      Vallejo, Enrique; Sanyal, Sutirtha; Harris, Tim; Vallejo, Fernando; Beivide, Ramón; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2011-06)
      Article
      Accés restringit per política de l'editorial
      Transactional Memory (TM) intends to simplify the design and implementation of the shared-memory data structures used in parallel software. Many Software TM systems are based on writer-locks to protect the data being ...