Ara es mostren els items 6-12 de 12

    • Impact of positive bias temperature instability (PBTI) 

      Aymerich Capdevila, Nivard; Ganapathy, Shrikanth; Rubio Sola, Jose Antonio; Canal Corretger, Ramon; González Colás, Antonio María (2011)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Memory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure ...
    • INFORMER: an integrated framework for early-stage memory robustness analysis 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Eric; González Colás, Antonio María; Rubio Sola, Jose Antonio (European Interactive Digital Advertising Alliance (EDAA), 2014)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      With the growing importance of parametric (process and environmental) variations in advanced technologies, it has become a serious challenge to design reliable, fast and low-power embedded memories. Adopting a variation-aware ...
    • iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Text en actes de congrés
      Accés obert
      Negative bias temperature instability (NBTI) is a major cause of concern for chip designers because of its inherent ability to drastically reduce silicon reliability over the lifetime of the processor. Coupled with statistical ...
    • MODEST: a model for energy estimation under spatio-temporal variability 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2010)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of the changing operating and environmental ...
    • On the effectiveness of hybrid mechanisms on reduction of parametric failures in caches 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2011-12-05)
      Report de recerca
      Accés restringit per política de l'editorial
      In this paper, we provide an insight on the different proactive read/write assist methods (wordline boosting & adaptive body biasing) that help in preventing (and reducing) parametric failures when coupled with reactive ...
    • Reliability in the face of variability in nanometer embedded memories 

      Ganapathy, Shrikanth (Universitat Politècnica de Catalunya, 2014-04-28)
      Tesi
      Accés obert
      In this thesis, we have investigated the impact of parametric variations on the behaviour of one performance-critical processor structure - embedded memories. As variations manifest as a spread in power and performance, ...
    • vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2010-09-05)
      Report de recerca
      Accés obert
      In this paper, we present an on-die post-silicon binning methodology that takes into account the effect of static and dynamic variations and categorizes every processor based on power/performance.The proposed scheme is ...