• Robust sequential circuits design technique for low voltage and high noise scenarios 

      García Leyva, Lancelot; Rivera Dueñas, Juan; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2016)
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      All electronic processing components in future deep nanotechnologies will exhibit high noise level and/ or low S/N ratios because of the extreme voltage reduction and the nearly erratic nature of such devices. ...
    • Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits 

      García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2010)
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      As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future technologies is to retain circuit ...
    • Turtle logic: Novel IC digital probabilistic design methodology 

      García Leyva, Lancelot; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja; Calomarde Palomino, Antonio (2010)
      Text en actes de congrés
      Accés obert
      Future electronic devices are expected to operate at lower voltage supply to save power, especially in ultimate and new technologies. The resulting reduction of logic levels approaches the thermal noise limit, and ...