• Metodología de diseño lógico redundante para escenarios con ruido extremadamente alto y bajo voltaje de alimentación 

      García Leyva, Lancelot (Universitat Politècnica de Catalunya, 2016-01-19)
      Tesi
      Accés obert
      In future scenarios of low power and low voltage the electronic systems will present a high error ratio or voltage fluctuations due to dramatically signal to noise ratio. These transient errors can affect the logical results ...
    • New redundant logic design concept for high noise and low voltage scenarios 

      García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Gómez Fernández, Sergio; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2011-12)
      Article
      Accés restringit per política de l'editorial
      This paper presents a new redundant logia design concept named Turtle Logic(TL).It is a new probabilistic logic method based on port redundancy and complementary data, oriented toward emerging technologies beyond CMOS, ...
    • Novel redundant logic design for noisy low voltage scenarios 

      García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2013)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      The concept worked in this paper named Turtle Logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging CMOS technologies and beyond, where the thermal noise could be ...
    • Robust sequential circuits design technique for low voltage and high noise scenarios 

      García Leyva, Lancelot; Rivera Dueñas, Juan; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2016)
      Text en actes de congrés
      Accés obert
      All electronic processing components in future deep nanotechnologies will exhibit high noise level and/ or low S/N ratios because of the extreme voltage reduction and the nearly erratic nature of such devices. ...
    • Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits 

      García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2010)
      Text en actes de congrés
      Accés obert
      As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future technologies is to retain circuit ...
    • Turtle logic: Novel IC digital probabilistic design methodology 

      García Leyva, Lancelot; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja; Calomarde Palomino, Antonio (2010)
      Text en actes de congrés
      Accés obert
      Future electronic devices are expected to operate at lower voltage supply to save power, especially in ultimate and new technologies. The resulting reduction of logic levels approaches the thermal noise limit, and ...