Exploració per autor "Pons Solé, Marc"

Ara es mostren els items 6-10 de 10

    • Layout regularity for design and manufacturability 

      Pons Solé, Marc (Universitat Politècnica de Catalunya, 2012-10-02)
      Tesi
      Accés obert
      In nowadays nanometer technology nodes, the semiconductor industry has to deal with the new challenges associated to technology scaling. On one hand, process developers face increasing manufacturing cost and variability, ...

    • Power supply noise and logic error probability 

      Andrade Miceli, Dennis Michael; Martorell Cid, Ferran; Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2007-08)
      Text en actes de congrés
      Accés obert
      Voltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing ...

    • Variations-aware circuit designs for microprocessors 

      Pons Solé, Marc (Centre de Publicacions del Campus Nord SCCL (CPET), 2009)
      Comunicació de congrés
      Accés obert

    • Variations-aware circuit designs for microprocessors 

      Pons Solé, Marc; Moll Echeto, Francisco de Borja; Abella Ferrer, Jaume (2010)
      Comunicació de congrés
      Accés obert
      A new trend that is becoming dominant is to improve layout regularity so that the layouts to be printed are more repetitive and easy to manufacture. Our proposal is to push to the limit layout regularity to minimize ...

    • VCTA: A Via-Configurable Transistor Array regular fabric 

      Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2010)
      Text en actes de congrés
      Accés obert
      Layout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper we focus on a scenario where layout regularity ...