Exploració per autor "Pons Solé, Marc"

Ara es mostren els items 1-10 de 10

    • Design of complex circuits using the via-configurable transistor array regular layout fabric 

      Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2011)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new ...

    • Energy macro-model for on chip interconnection buses 

      Mendoza Vázquez, Raymundo; Pons Solé, Marc; Moll Echeto, Francisco de Borja; Figueras, Joan (2006-06)
      Report de recerca
      Accés obert
      This report presents a fast method of evaluating the power consumption of a bus. Given an on-chip bus driver-interconnection-receiver design of N parallel lines,the objective is to develop its energy consumption macro-model. ...

    • Error probability in synchronous digital circuits due to power supply noise 

      Martorell Cid, Ferran; Pons Solé, Marc; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja (2007-09)
      Text en actes de congrés
      Accés obert
      This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits. The analysis here considered ...

    • Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study 

      González Colás, Antonio María; Pons Solé, Marc; Barajas Ojeda, Enrique; Mateo Peña, Diego; López González, Juan Miguel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier (IEEE Computer Society Publications, 2011)
      Comunicació de congrés
      Accés restringit per política de l'editorial
      Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated ...

    • FOCSI: A new layout regularity metric 

      Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (2009-06-09)
      Report de recerca
      Accés obert
      Digital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce ...

    • Layout regularity for design and manufacturability 

      Pons Solé, Marc (Universitat Politècnica de Catalunya, 2012-10-02)
      Tesi
      Accés obert
      In nowadays nanometer technology nodes, the semiconductor industry has to deal with the new challenges associated to technology scaling. On one hand, process developers face increasing manufacturing cost and variability, ...

    • Power supply noise and logic error probability 

      Andrade Miceli, Dennis Michael; Martorell Cid, Ferran; Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2007-08)
      Text en actes de congrés
      Accés obert
      Voltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing ...

    • Variations-aware circuit designs for microprocessors 

      Pons Solé, Marc (Centre de Publicacions del Campus Nord SCCL (CPET), 2009)
      Comunicació de congrés
      Accés obert

    • Variations-aware circuit designs for microprocessors 

      Pons Solé, Marc; Moll Echeto, Francisco de Borja; Abella Ferrer, Jaume (2010)
      Comunicació de congrés
      Accés obert
      A new trend that is becoming dominant is to improve layout regularity so that the layouts to be printed are more repetitive and easy to manufacture. Our proposal is to push to the limit layout regularity to minimize ...

    • VCTA: A Via-Configurable Transistor Array regular fabric 

      Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2010)
      Text en actes de congrés
      Accés obert
      Layout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper we focus on a scenario where layout regularity ...