Ara es mostren els items 9-16 de 16

    • On the simulation of large-scale architectures using multiple application abstraction levels 

      Rico Carro, Alejandro; Cabarcas, Felipe; Villavieja Prados, Carlos; Pavlovic, Milan; Vega, Augusto; Etsion, Yoav; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2012-01-23)
      Article
      Accés restringit per política de l'editorial
      Simulation is a key tool for computer architecture research. In particular, cycle-accurate simulators are extremely important for microarchitecture exploration and detailed design decisions, but they are slow and, so, not ...
    • Raising the level of abstraction : simulation of large chip multiprocessors running multithreaded applications 

      Rico Carro, Alejandro (Universitat Politècnica de Catalunya, 2013-10-29)
      Tesi
      Accés obert
      The number of transistors on an integrated circuit keeps doubling every two years. This increasing number of transistors is used to integrate more processing cores on the same chip. However, due to power density and ILP ...
    • Sampled simulation of task-based programs 

      Grass, Thomas; Carlson, Trevor E.; Rico Carro, Alejandro; Ceballos, Germán; Ayguadé Parra, Eduard; Casas, Marc; Moretó Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2019-02-01)
      Article
      Accés obert
      Sampled simulation is a mature technique for reducing simulation time of single-threaded programs. Nevertheless, current sampling techniques do not take advantage of other execution models, like task-based execution, to ...
    • Task management analysis on the CellBE 

      Rico Carro, Alejandro; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2008-09)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      There is a clear industrial trend towards chip multiprocessors (CMP) as the most power efficient way of further increasing performance. Heterogeneous CMP architectures take one more step along this power efficiency trend ...
    • Task superscalar: an out-of-order task pipeline 

      Etsion, Yoav; Cabarcas, Felipe; Rico Carro, Alejandro; Ramírez Bellido, Alejandro; Badia Sala, Rosa Maria; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (IEEE Computer Society Publications, 2010)
      Text en actes de congrés
      Accés obert
      We present Task Superscalar, an abstraction of instruction-level out-of-order pipeline that operates at the tasklevel. Like ILP pipelines, which uncover parallelism in a sequential instruction stream, task superscalar ...
    • Towards data-flow parallelization for adaptive mesh refinement applications 

      Sala Penadés, Kevin; Rico Carro, Alejandro; Beltran Querol, Vicenç (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Text en actes de congrés
      Accés obert
      Adaptive Mesh Refinement (AMR) is a prevalent method used by distributed-memory simulation applications to adapt the accuracy of their solutions depending on the turbulent conditions in each of their domain regions. These ...
    • Trace-driven simulation of multithreaded applications 

      Rico Carro, Alejandro; Duran González, Alejandro; Cabarcas, Felipe; Etsion, Yoav; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2011)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Over the past few years, computer architecture research has moved towards execution-driven simulation, due to the inability of traces to capture timing-dependent thread execution interleaving. However, trace-driven simulation ...
    • Vector architecture for HPC and ML 

      Rico Carro, Alejandro (Barcelona Supercomputing Center, 2018)
      Text en actes de congrés
      Accés obert