Exploració per autor "Moretó Planas, Miquel"
Ara es mostren els items 77-96 de 129
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PARSECSs: Evaluating the impact of task parallelism in the PARSEC benchmark suite
Chasapis, Dimitrios; Casas, Marc; Moretó Planas, Miquel; Vidal Ortiz, Raul; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (2015-12-01)
Article
Accés obertIn this work, we show how parallel applications can be implemented efficiently using task parallelism. We also evaluate the benefits of such parallel paradigm with respect to other approaches. We use the PARSEC benchmark ... -
Per-task energy accounting in computing systems
Liu, Qixiao; Jiménez, Víctor; Moretó Planas, Miquel; Abella Ferrer, Jaume; Cazorla, Francisco; Valero Cortés, Mateo (2013)
Report de recerca
Accés obertWe present for the first time the concept of per-task energy accounting (PTEA) and relate it to per-task energy metering (PTEM). We show the benefits of supporting both in future computing systems. Using the shared last-level ... -
Per-task energy metering and accounting in the multicore era
Liu, Qixiao; Moretó Planas, Miquel; Abell, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (Barcelona Supercomputing Center, 2015-05-05)
Text en actes de congrés
Accés obertEnergy has become arguably the most expensive resource in a computing system. As multi-core processors are the preferred processing platform across different computing domains, measuring the energy usage draws vast attention. ... -
Performance and energy effects on task-based parallelized applications: User-directed versus manual vectorization
Caminal Pallarés, Helena; Caballero de Gea, Diego; Cebrián González, Juan Manuel; Ferrer, Roger; Casas, Marc; Moretó Planas, Miquel; Martorell Bofill, Xavier; Valero Cortés, Mateo (2018-06)
Article
Accés obertHeterogeneity, parallelization and vectorization are key techniques to improve the performance and energy efficiency of modern computing systems. However, programming and maintaining code for these architectures poses a ... -
Peripheral twists for torus topologies with arbitrary aspect ratio
Vallejo Gutiérrez, Enrique; Moretó Planas, Miquel; Martínez, Carmen; Beivide Palacio, Julio Ramón (2011)
Text en actes de congrés
Accés obertA torus is a common topology used in supercomputer networks. Asymmetric Tori suffer from resource usage imbalance, which translates to reduced performance. Twisted Tori employ a twist in the peripheral links of one or more ... -
PIugSMART: a pluggable open-source module to implement multihop bypass in networks-on-chip
Monemi, Alireza; Pérez Gallardo, Iván; Leyva Santes, Neiel; Vallejo Gutiérrez, Enrique; Beivide Palacio, Julio Ramon; Moretó Planas, Miquel (Association for Computing Machinery (ACM), 2021)
Text en actes de congrés
Accés obertThe integration of many processing elements per die makes it more difficult to provide low latency in the Network-on-Chip (NoC). Multihop bypass proposals, such as SMART, attack this problem by allowing flits to skip ... -
PLANAR: a programmable accelerator for near-memory data rearrangement
Barredo Ferreira, Adrián; Armejach Sanosa, Adrià; Beard, Jonathan C.; Moretó Planas, Miquel (Association for Computing Machinery (ACM), 2021)
Text en actes de congrés
Accés obertMany applications employ irregular and sparse memory accesses that cannot take advantage of existing cache hierarchies in high performance processors. To solve this problem, Data Layout Transformation (DLT) techniques ... -
Porting and optimizing BWA-MEM2 using the Fujitsu A64FX processor
Langarita Benítez, Rubén; Armejach Sanosa, Adrià; Ibáñez Marín, Pablo; Alastruey Benedé, Jesús; Moretó Planas, Miquel (2023-09)
Article
Accés obertSequence alignment pipelines for human genomes are an emerging workload that will dominate in the precision medicine field. BWA-MEM2 is a tool widely used in the scientific community to perform read mapping studies. In ... -
POSTER: Exploiting asymmetric multi-core processors with flexible system sofware
Chronaki, Kallia; Moretó Planas, Miquel; Casas, Marc; Rico, Alejandro; Badia Sala, Rosa Maria; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2016)
Comunicació de congrés
Accés obertEnergy efficiency has become the main challenge for high performance computing (HPC). The use of mobile asymmetric multi-core architectures to build future multi-core systems is an approach towards energy savings while ... -
POSTER: SPiDRE: accelerating sparse memory access patterns
Barredo Ferreira, Adrián; Beard, Jonathan C.; Moretó Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2019)
Comunicació de congrés
Accés obertDevelopment in process technology has led to an exponential increase in processor speed and memory capacity. However, memory latencies have not improved as dramatically and represent a well-known problem in computer ... -
Power efficient job scheduling by predicting the impact of processor manufacturing variability
Chasapis, Dimitrios; Moretó Planas, Miquel; Schulz, Martin; Rountree, Barry; Valero Cortés, Mateo; Casas, Marc (Association for Computing Machinery (ACM), 2019)
Text en actes de congrés
Accés obertModern CPUs suffer from performance and power consumption variability due to the manufacturing process. As a result, systems that do not consider such variability caused by manufacturing issues lead to performance degradations ... -
PrioRAT: criticality-driven prioritization inside the on-chip memory hierarchy
Dimic, Vladimir; Moretó Planas, Miquel; Casas, Marc; Valero Cortés, Mateo (Springer Nature, 2021)
Text en actes de congrés
Accés obertThe ever-increasing gap between the processor and main memory speeds requires careful utilization of the limited memory link. This is additionally emphasized for the case of memory-bound applications. Prioritization of ... -
Reducing cache coherence traffic with a NUMA-aware runtime approach
Caheny, Paul; Álvarez Martí, Lluc; Derradji, Said; Valero Cortés, Mateo; Moretó Planas, Miquel; Casas, Marc (2018-05)
Article
Accés obertCache Coherent NUMA (ccNUMA) architectures are a widespread paradigm due to the benefits they provide for scaling core count and memory capacity. Also, the flat memory address space they offer considerably improves ... -
Reducing cache coherence traffic with hierarchical directory cache and NUMA-aware runtime scheduling
Caheny, Paul; Casas, Marc; Moretó Planas, Miquel; Gloaguen, Hervé; Saintes, Maxime; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertCache Coherent NUMA (ccNUMA) architectures are a widespread paradigm due to the benefits they provide for scaling core count and memory capacity. Also, the flat memory address space they offer considerably improves ... -
Reducing data movement on large shared memory systems by exploiting computation dependencies
Barrera, I.S.; Ayguadé Parra, Eduard; Valero Cortés, Mateo; Moretó Planas, Miquel; Labarta Mancho, Jesús José; Casas, Marc (Association for Computing Machinery (ACM), 2018)
Text en actes de congrés
Accés obertShared memory systems are becoming increasingly complex as they typically integrate several storage devices. That brings different access latencies or bandwidth rates depending on the proximity between the cores where ... -
RICH: implementing reductions in the cache hierarchy
Dimic, Vladimir; Moretó Planas, Miquel; Casas, Marc; Ciesko, Jan; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2020)
Text en actes de congrés
Accés obertReductions constitute a frequent algorithmic pattern in high-performance and scientific computing. Sophisticated techniques are needed to ensure their correct and scalable concurrent execution on modern processors. Reductions ... -
RISC-V for genome data analysis: opportunities and challenges
López Villellas, Lorien; Pineda Sánchez, Esteve; Badouh, Asaf; Marco-Sola, Santiago; Ibáñez Marín, Pablo; Alastruey Benedé, Jesús; Moretó Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertThe RISC-V ISA has gained significant momentum in High-Performance Computing (HPC) research and market due to its open-source nature, fostering collaborative research and innovation. The ever-growing RISC-V-based ... -
Runtime-assisted cache coherence deactivation in task parallel programs
Caheny, Paul; Álvarez Martí, Lluc; Valero Cortés, Mateo; Moretó Planas, Miquel; Casas, Marc (Association for Computing Machinery (ACM), 2018)
Text en actes de congrés
Accés obertWith increasing core counts, the scalability of directory-based cache coherence has become a challenging problem. To reduce the area and power needs of the directory, recent proposals reduce its size by classifying data ... -
Runtime-assisted shared cache insertion policies based on re-reference intervals
Dimic, Vladimir; Moretó Planas, Miquel; Casas, Marc; Valero Cortés, Mateo (Springer, 2017)
Text en actes de congrés
Accés obertProcessor speed is improving at a faster rate than the speed of main memory, which makes memory accesses increasingly expensive. One way to solve this problem is to reduce miss ratio of the processor’s last level cache by ... -
Runtime-aware architectures
Casas, Marc; Moretó Planas, Miquel; Álvarez Martí, Lluc; Castillo Villar, Emilio; Chasapis, Dimitrios; Hayes, Timothy; Jaulmes, Luc; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Springer, 2015)
Text en actes de congrés
Accés obertIn the last few years, the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore’s Law have vanished. When uni-cores were the norm, hardware design was decoupled from the software ...