Ara es mostren els items 35-54 de 129

    • Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies 

      Barredo Ferreira, Adrián; Cebrián González, Juan Manuel; Valero Cortés, Mateo; Casas, Marc; Moretó Planas, Miquel (2020-03)
      Article
      Accés obert
      Moore’s Law predicted that the number of transistors on a chip would double approximately every 2 years. However, this trend is arriving at an impasse. Optimizing the usage of the available transistors within the thermal ...
    • Enabling hardware randomization across the cache hierarchy in Linux-Class processors 

      Doblas, Max; Kostalampros, Ioannis-Vatistas; Moretó Planas, Miquel; Hernández Luz, Carles (2020)
      Text en actes de congrés
      Accés obert
      The most promising secure-cache design approaches use cache-set randomization to index cache contents thus thwarting cache side-channel attacks. Unfortunately, existing randomization proposals cannot be sucessfully applied ...
    • Evaluating execution time predictability of task-based programs on multi-core processors 

      Grass, Thomas Dieter; Rico Carro, Alejandro; Casas, Marc; Moretó Planas, Miquel; Ramírez Bellido, Alejandro (Springer, 2015)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Task-based programming models are becoming increasingly important, as they can reduce the synchronization costs of parallel programs on multi-cores. Instances of the same task type in task-based programs consist of the ...
    • Evaluating scientific workflow execution on an asymmetric multicore processor 

      Pietri, Ilia; Zhuang, Sicong; Casas, Marc; Moretó Planas, Miquel; Sakellariou, Rizos (Springer, 2018-02)
      Comunicació de congrés
      Accés obert
      Asymmetric multicore architectures that integrate different types of cores are emerging as a potential solution for good performance and power efficiency. Although scheduling can be improved by utilizing an appropriate set ...
    • Evaluating the impact of OpenMP 4.0 extensions on relevant parallel workloads 

      Vidal Ortiz, Raul; Casas, Marc; Moretó Planas, Miquel; Chasapis, Dimitrios; Ferrer Ibáñez, Roger; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Springer, 2015)
      Text en actes de congrés
      Accés obert
      OpenMP has been for many years the most widely used programming model for shared memory architectures. Periodically, new features are proposed and some of them are finally selected for inclusion in the OpenMP standard. The ...
    • Evolutionary system for prediction and optimization of hardware architecture performance 

      Castillo, Pedro Angel; Merelo, Juan Julián; Moretó Planas, Miquel; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo; Mora, Antonio; Laredo, Juan Luís; McKee, Sally (2008-06)
      Text en actes de congrés
      Accés obert
      The design of computer architectures is a very complex problem. The multiple parameters make the number of possible combinations extremely high. Many researchers have used simulation, although it is a slow solution since ...
    • Explaining dynamic cache partitioning speed ups 

      Moretó Planas, Miquel; Cazorla, Francisco; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2007-01)
      Article
      Accés obert
      Cache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, ...
    • Exploiting asynchrony from exact forward recovery for DUE in iterative solvers 

      Jaulmes, Luc; Casas, Marc; Moretó Planas, Miquel; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (2015)
      Report de recerca
      Accés obert
      This paper presents a method to protect iterative solvers from Detected and Uncorrected Errors (DUE) relying on error detection techniques already available in commodity hardware. Detection operates at the memory page ...
    • Exploiting asynchrony from exact forward recovery for DUE in iterative solvers 

      Jaulmes, Luc; Casas, Marc; Moretó Planas, Miquel; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2015)
      Text en actes de congrés
      Accés obert
      This paper presents a method to protect iterative solvers from Detected and Uncorrected Errors (DUE) relying on error detection techniques already available in commodity hardware. Detection operates at the memory page ...
    • Exploration of architectural parameters for future HPC systems 

      Gómez, Constantino; Martínez, Francesc; Armejach Sanosa, Adrià; Casas, Marc; Mantovani, Filippo; Moretó Planas, Miquel (Barcelona Supercomputing Center, 2019-05-07)
      Text en actes de congrés
      Accés obert
    • Fast behavioural RTL simulation of 10B transistor SoC designs with Metro-Mpi 

      López Paradís, Guillem; Li, Brian; Armejach Sanosa, Adrià; Wallentowitz, Stefan; Moretó Planas, Miquel; Balkind, Jonathan (Institute of Electrical and Electronics Engineers (IEEE), 2023)
      Text en actes de congrés
      Accés obert
      Chips with tens of billions of transistors have become today's norm. These designs are straining our electronic design automation tools throughout the design process, requiring ever more computational resources. In many ...
    • Fast gap-affine pairwise alignment using the wavefront algorithm 

      Marco-Sola, Santiago; Moure López, Juan Carlos; Moretó Planas, Miquel; Espinosa Morales, Antonio (2020-09-11)
      Article
      Accés obert
      Motivation Pairwise alignment of sequences is a fundamental method in modern molecular biology, implemented within multiple bioinformatics tools and libraries. Current advances in sequencing technologies press for the ...
    • Functional verification of a RISC-V vector accelerator 

      Jiménez Arador, Víctor; Rodriguez, Mario; Dominguez de la Rocha, Marc; Sans, Josep; Díaz Ortega, Iván; Valente, Luca; Guglielmi, Vito Luca; Quiroga Esparza, Josué Vladimir; Genovese, Roberto Ignacio; Sonmez, Nehir; Palomar Pérez, Óscar; Moretó Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2023-06)
      Article
      Accés obert
      We present the functional verification efforts for an academic RISC-V based vector accelerator, successfully taped-out in the context of the European Processor Initiative. For our novel RISC-V based decoupled vector ...
    • gem5 + rtl: A framework to enable RTL models inside a full-system simulator 

      López Paradís, Guillem; Armejach Sanosa, Adrià; Moretó Planas, Miquel (Association for Computing Machinery (ACM), 2021)
      Text en actes de congrés
      Accés obert
      In recent years there has been a surge of interest in designing custom accelerators for power-efficient high-performance computing. However, available tools to simulate low-level RTL designs often neglect the target system ...
    • GMX: Instruction set extensions for fast, scalable, and efficient genome sequence alignment 

      Doblas Font, Max; Lostes Cazorla, Oscar; Aguado Puig, Quim; Cebry, Nicholas; Fontova Muste, Pau; Batten, Christopher; Marco Sola, Santiago; Moretó Planas, Miquel (Association for Computing Machinery (ACM), 2023)
      Text en actes de congrés
      Accés obert
      Sequence alignment remains a fundamental problem in computer science with practical applications ranging from pattern matching to computational biology. The ever-increasing volumes of genomic data produced by modern DNA ...
    • Graph partitioning applied to DAG scheduling to reduce NUMA effects 

      Sánchez Barrera, Isaac; Casas, Marc; Moretó Planas, Miquel; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2018)
      Comunicació de congrés
      Accés obert
      The complexity of shared memory systems is becoming more relevant as the number of memory domains increases, with different access latencies and bandwidth rates depending on the proximity between the cores and the devices ...
    • HLS-based HW/SW co-design of the post-quantum classic McEliece cryptosystem 

      Kostalabros, Vatistas; Ribes González, Jordi; Farràs Ventura, Oriol; Moretó Planas, Miquel; Hernández Luz, Carles (Institute of Electrical and Electronics Engineers (IEEE), 2021)
      Text en actes de congrés
      Accés obert
      While quantum computers are rapidly becoming more powerful, the current cryptographic infrastructure is imminently threatened. In a preventive manner, the U.S. National Institute of Standards and Technology (NIST) has ...
    • How can we improve energy efficiency through user-directed vectorization and task-based parallelization? 

      Caminal, Helena; Caballero, Diego; Cebrián, Juan M.; Ferrer, Roger; Casas, Marc; Moretó Planas, Miquel; Martorell Bofill, Xavier; Valero Cortés, Mateo (Barcelona Supercomputing Center, 2015-05-05)
      Text en actes de congrés
      Accés obert
      Heterogeneity, parallelization and vectorization are key techniques to improve the performance and energy efficiency of modern computing systems. However, programming and maintaining code for these architectures poses a ...
    • Improving cache Behavior in CMP architectures throug cache partitioning techniques 

      Moretó Planas, Miquel (Universitat Politècnica de Catalunya, 2010-03-19)
      Tesi
      Accés obert
      The evolution of microprocessor design in the last few decades has changed significantly, moving from simple inorder single core architectures to superscalar and vector architectures in order to extract the maximum available ...
    • Improving predication efficiency through compaction/restoration of SIMD instructions 

      Barredo Ferreira, Adrián; Cebrián González, Juan Manuel; Moretó Planas, Miquel; Casas, Marc; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Text en actes de congrés
      Accés obert
      Vector processors offer a wide range of unexplored opportunities to improve performance and energy efficiency. However, despite its potential, vector code generation and execution have significant challenges, the most ...