Exploració per autor "Moretó Planas, Miquel"
Ara es mostren els items 21-40 de 129
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BST: A BookSim-based toolset to simulate NoCs with single- and multi-hop bypass
Pérez Gallardo, Iván; Vallejo Gutiérrez, Enrique; Moretó Planas, Miquel; Beivide Palacio, Julio Ramon (Institute of Electrical and Electronics Engineers (IEEE), 2020)
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Accés obertNetwork-on-Chips are a critical part of modern multiprocessors and their relevance will grow with the number of cores. The development of future NoC designs relies on detailed simulation models that accurately estimate ... -
CATA: Criticality aware task acceleration for multicore processors
Castillo, Emilio; Moretó Planas, Miquel; Casas, Marc; Álvarez Martí, Lluc; Vallejo, Enrique; Chronaki, Kallia; Badia Sala, Rosa Maria; Bosque Orero, José Luis; Beivide Palacio, Julio Ramón; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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Accés obertManaging criticality in task-based programming models opens a wide range of performance and power optimization opportunities in future manycore systems. Criticality aware task schedulers can benefit from these opportunities ... -
Characterization of a coherent hardware accelerator framework for SoCs
López Paradís, Guillem; Venu, Balaji; Armejach Sanosa, Adrià; Moretó Planas, Miquel (Springer, 2023)
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Accés restringit per política de l'editorialAccelerators rich architectures have become the standard in today’s SoCs. After Moore’s law diminish, it is common to only dedicate a fraction of the area of the SoC to traditional cores and leave the rest of space for ... -
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
Álvarez Martí, Lluc; Vilanova, Lluís; Moretó Planas, Miquel; Casas, Marc; González Tallada, Marc; Martorell Bofill, Xavier; Navarro, Nacho; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2015)
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Accés obertThe increasing number of cores in manycore architectures causes important power and scalability problems in the memory subsystem. One solution is to introduce scratchpad memories alongside the cache hierarchy, forming a ... -
Compiler-assisted compaction/restoration of SIMD instructions
Cebrián González, Juan Manuel; Balem, Thibaud; Barredo Ferreira, Adrián; Casas, Marc; Moretó Planas, Miquel; Ros Bardisa, Alberto; Jimborean, Alexandra (2022-04-01)
Article
Accés obertAll the supercomputers in the world exploit data-level parallelism (DLP), for example by using single instructions to operate over several data elements. Improving vector processing is therefore key for exascale computing. ... -
Compressed sparse FM-index: Fast sequence alignment using large K-steps
Langarita Benítez, Rubén; Armejach Sanosa, Adrià; Setoain, Javier; Ibáñez Marín, Pablo Enrique; Alastruey Benedé, Jesús; Moretó Planas, Miquel (2022-01-01)
Article
Accés obertThe FM-index is a data structure used in genomics for exact search of input sequences over large reference genomes. Algorithms based on the FM-index show an irregular memory access pattern, resulting in a memory bound ... -
CPU accounting in CMP processors
Luque, Carlos; Moretó Planas, Miquel; Cazorla, Francisco; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo (2009-01)
Article
Accés obertChip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ... -
Data prefetching on in-order processors
Ortega Carrasco, Cristobal; García Flores, Víctor; Moretó Planas, Miquel; Casas, Marc; Rositoru, Roxana (Institute of Electrical and Electronics Engineers (IEEE), 2018)
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Accés obertLow-power processors have attracted attention due to their energy-efficiency. A large market, such as the mobile one, relies on these processors for this very reason. Even High Performance Computing (HPC) systems are ... -
Design space exploration of next-generation HPC machines
Gómez Crespo, Constantino; Martínez Palau, Francesc; Armejach Sanosa, Adrià; Moretó Planas, Miquel; Mantovani, Filippo; Casas, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2019)
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Accés restringit per acord de confidencialitatThe landscape of High Performance Computing (HPC) system architectures keeps expanding with new technologies and increased complexity. With the goal of improving the efficiency of next-generation large HPC systems, designers ... -
Design trade-offs for emerging HPC processors based on mobile market technology
Armejach Sanosa, Adrià; Casas, Marc; Moretó Planas, Miquel (2019-09-01)
Article
Accés obertHigh-performance computing (HPC) is at the crossroads of a potential transition toward mobile market processor technology. Unlike in prior transitions, numerous hardware vendors and integrators will have access to ... -
DReAM: An approach to estimate per-Task DRAM energy in multicore systems
Liu, Qixiao; Moretó Planas, Miquel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (2016-12)
Article
Accés obertAccurate per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is ... -
DReAM: Per-task DRAM energy metering in multicore systems
Liu, Qixiao; Moretó Planas, Miquel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (Springer, 2014)
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Accés obertInteraction across applications in DRAM memory impacts its energy consumption. This paper makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations, ... -
DVINO: A RISC-V vector processor implemented in 65nm technology
Cabo Pitarch, Guillem; Candon, Gerard; Carril, Xavier; Doblas Font, Max; Dominguez de la Rocha, Marc; González Trejo, Alberto; Hernández Calderón, César Alejandro; Jiménez Arador, Víctor; Kostalampros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel Israel; López Paradís, Guillem; Mendoza Escobar, Jonnatan; Minervini Minervini, Francesco; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Rodas, Narcis; Reggiani, Enrico; Rodriguez, Mario; Rojas Morales, Carlos; Ruíz Ramírez, Abraham Josafat; Soria Pardos, Víctor; Vargas Valdivieso, Iván; Figueras Bagué, Roger; Fontova, Pau; Marimon Illana, Joan; Montabes, Víctor; Cristal Kestelman, Adrián; Hernández Luz, Carles; Moretó Planas, Miquel; Moll Echeto, Francisco de Borja; Palomar Pérez, Óscar; Rubio Sola, Jose Antonio; Sonmez, Nehir; Unsal, Osman Sabri; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2022)
Comunicació de congrés
Accés obertThis paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM ... -
DynAMO: Improving parallelism through dynamic placement of atomic memory operations
Soria Pardos, Víctor; Armejach Sanosa, Adrià; Mück, Tiago; Suárez Gracía, Dario; Joao, Jose A.; Rico, Alejandro; Moretó Planas, Miquel (Association for Computing Machinery (ACM), 2023)
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Accés obertWith increasing core counts in modern multi-core designs, the overhead of synchronization jeopardizes the scalability and efficiency of parallel applications. To mitigate these overheads, modern cache-coherent protocols ... -
Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies
Barredo Ferreira, Adrián; Cebrián González, Juan Manuel; Valero Cortés, Mateo; Casas, Marc; Moretó Planas, Miquel (2020-03)
Article
Accés obertMoore’s Law predicted that the number of transistors on a chip would double approximately every 2 years. However, this trend is arriving at an impasse. Optimizing the usage of the available transistors within the thermal ... -
Enabling hardware randomization across the cache hierarchy in Linux-Class processors
Doblas, Max; Kostalampros, Ioannis-Vatistas; Moretó Planas, Miquel; Hernández Luz, Carles (2020)
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Accés obertThe most promising secure-cache design approaches use cache-set randomization to index cache contents thus thwarting cache side-channel attacks. Unfortunately, existing randomization proposals cannot be sucessfully applied ... -
Evaluating execution time predictability of task-based programs on multi-core processors
Grass, Thomas Dieter; Rico Carro, Alejandro; Casas, Marc; Moretó Planas, Miquel; Ramírez Bellido, Alejandro (Springer, 2015)
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Accés restringit per política de l'editorialTask-based programming models are becoming increasingly important, as they can reduce the synchronization costs of parallel programs on multi-cores. Instances of the same task type in task-based programs consist of the ... -
Evaluating scientific workflow execution on an asymmetric multicore processor
Pietri, Ilia; Zhuang, Sicong; Casas, Marc; Moretó Planas, Miquel; Sakellariou, Rizos (Springer, 2018-02)
Comunicació de congrés
Accés obertAsymmetric multicore architectures that integrate different types of cores are emerging as a potential solution for good performance and power efficiency. Although scheduling can be improved by utilizing an appropriate set ... -
Evaluating the impact of OpenMP 4.0 extensions on relevant parallel workloads
Vidal Ortiz, Raul; Casas, Marc; Moretó Planas, Miquel; Chasapis, Dimitrios; Ferrer Ibáñez, Roger; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Springer, 2015)
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Accés obertOpenMP has been for many years the most widely used programming model for shared memory architectures. Periodically, new features are proposed and some of them are finally selected for inclusion in the OpenMP standard. The ... -
Evolutionary system for prediction and optimization of hardware architecture performance
Castillo, Pedro Angel; Merelo, Juan Julián; Moretó Planas, Miquel; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo; Mora, Antonio; Laredo, Juan Luís; McKee, Sally (2008-06)
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Accés obertThe design of computer architectures is a very complex problem. The multiple parameters make the number of possible combinations extremely high. Many researchers have used simulation, although it is a slow solution since ...