Ara es mostren els items 16-30 de 30

    • MT-SBST: self-test optimization in multithreaded multicore architectures 

      Foutris, Nikos; Psarakis, M.; Gizopoulos, Dimitris; Apostolakis, A.; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2010)
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      Instruction-based or software-based self-testing (SBST) is a scalable functional testing paradigm that has gained increasing acceptance in testing of single-threaded uniprocessors. Recent computer architecture trends towards ...
    • Near-optimal loop tiling by means of cache miss equations and genetic algorithms 

      Abella Ferrer, Jaume; González Colás, Antonio María; Llosa Espuny, José Francisco; Vera Rivera, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2002)
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      The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transformations such as loop tiling, which is a ...
    • On-line failure detection and confinement in caches 

      Abella Ferrer, Jaume; Chaparro, Pedro; Vera Rivera, Francisco Javier; Carretero Casado, Javier Sebastián; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2008)
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      Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which increases in-the-field error rate due to both latent defects and actual errors. As a consequence, there is an increasing need ...
    • Online error detection and correction of erratic bits in register files 

      Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; Carretero Casado, Javier Sebastián; Chaparro Valero, Pedro Alonso; González Colás, Antonio María (2009-06)
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      Aggressive voltage scaling needed for low power in each new process generation causes large deviations in the threshold voltage of minimally sized devices of the 6T SRAM cell. Gate oxide scaling can cause large transient ...
    • Optimizing program locality through CMEs and GAs 

      Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; González Colás, Antonio María; Llosa Espuny, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2003)
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      Caches have become increasingly important with the widening gap between main memory and processor speeds. Small and fast cache memories are designed to bridge this discrepancy. However, they are only effective when programs ...
    • Penelope: The NBTI-aware processor 

      Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society, 2007)
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      Transistors consist of lower number of atoms with every technology generation. Such atoms may be displaced due to the stress caused by high temperature, frequency and current, leading to failures. NBTI (negative bias ...
    • Reducing DUE-FIT of caches by exploiting acoustic wave detectors for error recovery 

      Upasani, Gaurang; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2013)
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      Cosmic radiation induced soft errors have emerged as a key challenge in computer system design. The exponential increase in the transistor count will drive the per chip fault rate sky high. New techniques for detecting ...
    • Reducing soft errors through operand width aware policies 

      Ergin, Oguz; Unsal, Osman Sabri; Vera Rivera, Francisco Javier; González Colás, Antonio María (2009-09)
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      Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. ...
    • Refueling: Preventing wire degradation due to electromigration 

      Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; Unsal, Osman Sabri; Ergin, Oguz; González Colás, Antonio María; Tschanz, James W. (2008-12)
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      Electromigration is a major source of wire and via failure. Refueling undoes EM for bidirectional wires and power/ground grids-some of a chip's most vulnerable wires. Refueling exploits EM's self-healing effect by balancing ...
    • Selective replication: a lightweight technique for soft errors 

      Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; Carretero Casado, Javier Sebastián; González Colás, Antonio María (ACM Press. Association for Computing Machinery, 2009-12)
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      Soft errors are an important challenge in contemporary microprocessors. Modern processors have caches and large memory arrays protected by parity or error detection and correction codes. However, today’s failure rate is ...
    • Setting an error detection infrastructure with low cost acoustics wave detectors 

      Upasani, Gaurang; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE, 2012)
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      The continuing decrease in dimensions and operating voltage of transistors has increased their sensitivity against radiation phenomena making soft errors an important challenge in future chip multiprocessors (CMPs). Hence, ...
    • TRAMS Project: variability and reliability of SRAM memories in sub-22nm bulk-CMOS technologies 

      Canal Corretger, Ramon; Rubio Sola, Jose Antonio; ASenov, Asen; Brown, Andrew; Miranda, Miguel; Zuber, Paul; González Colás, Antonio María; Vera Rivera, Francisco Javier (Elsevier, 2011-12-22)
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      The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this ...
    • Variable-based multi-module data caches for clustered VLIW processors 

      Gibert Codina, Enric; Abella Ferrer, Jaume; Sánchez Navarro, Jesús; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2005)
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      Memory structures consume an important fraction of the total processor energy. One solution to reduce the energy consumed by cache memories consists of reducing their supply voltage and/or increase their threshold voltage ...
    • VCTA: A Via-Configurable Transistor Array regular fabric 

      Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2010)
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      Layout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper we focus on a scenario where layout regularity ...
    • Via-configurable transistors array: a regular design technique to improve ICs yield 

      Pons, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2007)
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      Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our ...