Exploració per autor "Cazorla Almeida, Francisco Javier"
Ara es mostren els items 119-138 de 145
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TASA: toolchain-agnostic static software randomisation for critical real-time systems
(Association for Computing Machinery (ACM), 2016)
Text en actes de congrés
Accés obertMeasurement-Based Probabilistic Timing Analysis (MBPTA) derives WCET estimates for tasks running on processors comprising high-performance features such as caches. MBPTA's correct application requires the system to exhibit ... -
The next convergence: High-performance and mission-critical markets
(2013)
Text en actes de congrés
Accés obertThe well-known convergence of the high-performance computing and the mobile markets has been a dominating factor in the computing market during the last two decades. In this paper we witness a new type of convergence between ... -
Thread assignment in multicore/multithreaded processors: A statistical approach
(2016-01-01)
Article
Accés obertThe introduction of multicore/multithreaded processors, comprised of a large number of hardware contexts (virtual CPUs) that share resources at multiple levels, has made process scheduling, in particular assignment of ... -
Thread assignment of multithreaded network applications in multicore/multithreaded processors
(2013-12)
Article
Accés obertThe introduction of multithreaded processors comprised of a large number of cores with many shared resources makes thread scheduling, and in particular optimal assignment of running threads to processor hardware contexts ... -
Thread to core assignment in SMT on-chip multiprocessors
(IEEE Computer Society Publications, 2009)
Text en actes de congrés
Accés obertState-of-the-art high-performance processors like the IBM POWER5 and Intel i7 show a trend in industry towards on-chip Multiprocessors (CMP) involving Simultaneous Multithreading (SMT) in each core. In these processors, ... -
Thread to core assignment in SMT on-chip multiprocessors
(2009)
Article
Accés obertState-of-the-art high-performance processors like the IBM POWER5 and Intel i7 show a trend in industry towards on-chip Multiprocessors (CMP) involving Simultaneous Multithreading (SMT) in each core. In these processors, ... -
Thread to strand binding of parallel network applications in massive multi-threaded systems
(2010-05)
Article
Accés restringit per política de l'editorialIn processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a single level of resource sharing, such as pure-SMT ... -
Thread to strand binding of parallel network applications in massive multi-threaded systems
(ACM Press. Association for Computing Machinery, 2010-01)
Text en actes de congrés
Accés restringit per política de l'editorialIn processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a single level of resource sharing, such as pure-SMT ... -
Time-analysable non-partitioned shared caches for real-time multicore systems
(Association for Computing Machinery (ACM), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialShared caches in multicores challenge Worst-Case Execution Time (WCET) estimation due to inter-task interferences. Hard-ware and software cache partitioning address this issue although they complicate data sharing among ... -
Timing of autonomous driving software: problem analysis and prospects for future solutions
(IEEE, 2020)
Text en actes de congrés
Accés obertThe software used to implement advanced functionalities in critical domains (e.g. autonomous operation) impairs software timing. This is not only due to the complexity of the underlying high-performance hardware deployed ... -
Towards functional safety compliance of matrix–matrix multiplication for machine learning-based autonomous systems
(2021-12)
Article
Accés obertAutonomous systems execute complex tasks to perceive the environment and take self-aware decisions with limited human interaction. This autonomy is commonly achieved with the support of machine learning algorithms. The ... -
Towards limiting the impact of timing anomalies in complex real-time processors
(2019)
Text en actes de congrés
Accés obertTiming verification of embedded critical real-time systems is hindered by complex designs. Timing anomalies, deeply analyzed in static timing analysis, require specific solutions to bound their impact. For the first time, ... -
Tracing Hardware Monitors in the GR712RC Multicore Platform: Challenges and Lessons Learnt from a Space Case Study
(Schloss Dagstuhl – Leibniz-Zentrum für Informatik, 2020)
Comunicació de congrés
Accés obertThe demand for increased computing performance is driving industry in critical-embedded systems (CES) domains, e.g. space, towards the use of multicores processors. Multicores, however, pose several challenges that must ... -
Tracking coherence-related contention delays in real-time multicore systems
(Association for Computing Machinery (ACM), 2023)
Text en actes de congrés
Accés obertThe prevailing use of multicores in Embedded Critical Systems (ECS) is multi-application workloads in which independent applications run in different cores with data sharing restricted to the communication between applications ... -
Unboxing the sand: on deploying safety measures in the programmable logic of COTS MPSoCs
(Association Aéronautique et Astronautique de France (3AF), 2022)
Text en actes de congrés
Accés obertThe lack of sufficient hardware support for functional safety precludes the full adoption of many Commercial Off-the-Shelf (COTS) MPSoCs in safety-related systems, such as those in the aerospace industry. Some recent MPSoCs ... -
Uncertainty Management in Dependable and Intelligent Embedded Software
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Article
Accés obertThe development of dependable and intelligent embedded systems progresses. However, integrating complex software stacks, machine learning solutions, and high-performance computing devices amplifies the functional and ... -
Understanding and exploiting the internals of GPU resource allocation for critical systems
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertCritical real-time systems require strict resource provisioning in terms of memory and timing. The constant need for higher performance in these systems has led industry to recently include GPUs. However, GPU software ... -
Understanding the overhead of the spin-lock loop in CMT architectures
(2008)
Text en actes de congrés
Accés obertSpin locks are a synchronization mechanisms used to provide mutual exclusion to shared software resources. Spin locks are used over other synchronization mechanisms in several situations, like when the average waiting ... -
UP2DATE: Safe and secure over-the-air software updates on high-performance mixed-criticality systems
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Comunicació de congrés
Accés obertFollowing the same trend of consumer electronics, safety-critical industries are starting to adopt Over-The-Air Software Updates (OTASU) on their embedded systems. The motivation behind this trend is twofold. On the one ... -
Using Markov’s inequality with power-of-k function for probabilistic WCET estimation
(Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2022)
Text en actes de congrés
Accés obertDeriving WCET estimates for software programs with probabilistic means (a.k.a. pWCET estimation) has received significant attention during last years as a way to deal with the increased complexity of the processors used ...
