Exploració per autor "Cazorla Almeida, Francisco Javier"
Ara es mostren els items 93-112 de 145
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Per-task energy metering and accounting in the multicore era
(Barcelona Supercomputing Center, 2015-05-05)
Text en actes de congrés
Accés obertEnergy has become arguably the most expensive resource in a computing system. As multi-core processors are the preferred processing platform across different computing domains, measuring the energy usage draws vast attention. ... -
Performance analysis and optimization of automotive GPUs
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertAdvanced Driver Assistance Systems (ADAS) and Autonomous Driving (AD) have drastically increased the performance demands of automotive systems. Suitable highperformance platforms building upon Graphic Processing Units ... -
Performance analysis and optimization opportunities for NVIDIA automotive GPUs
(Elsevier, 2021-06)
Article
Accés obertAdvanced Driver Assistance Systems (ADAS) and Autonomous Driving (AD) bring unprecedented performance requirements for automotive systems. Graphic Processing Unit (GPU) based platforms have been deployed with the aim of ... -
PRL: standardizing performance monitoring library for high-integrity real-time systems
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés obertThe use of complex processors is becoming ubiquitous in High-Integrity Systems (HIS). To deal with processor’s increased complexity, Performance Monitoring Counters (PMCs) are increasingly used to reason on software behavior ... -
Probabilistic timing analysis on conventional cache designs
(2013)
Text en actes de congrés
Accés restringit per política de l'editorialProbabilistic timing analysis (PTA), a promising alternative to traditional worst-case execution time (WCET) analyses, enables pairing time bounds (named probabilistic WCET or pWCET) with an exceedance probability (e.g., ... -
Probabilistically time-analyzable complex processors in hard real- time systems
(Barcelona Supercomputing Center, 2015-05-05)
Text en actes de congrés
Accés obertCritical Real-Time Embedded Systems (CRTES) feature performance-demanding functionality. High-performance hardware and complex software can provide such functionality, but the use of aggressive technology challenges ... -
pTNoC: Probabilistically time-analyzable tree-based NoC for mixed-criticality systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertThe use of networks-on-chip (NoC) in real-time safety-critical multicore systems challenges deriving tight worst-case execution time (WCET) estimates. This is due to the complexities in tightly upper-bounding the contention ... -
QoS for high-performance SMT processors in embedded systems
(2004-07)
Article
Accés obertAlthough simultaneous multithreading processors provide a good cost-performance tradeoff, they exhibit unpredictable performance in real-time applications. We present a resource management scheme that eliminates a major ... -
Quasi Isolation QoS Setups to Control MPSoC Contention in Integrated Software Architectures
(Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2023)
Comunicació de congrés
Accés obertThe use of integrated architectures, such as integrated modular avionics (IMA) in avionics, IMA-SP in space, and AUTOSAR in automotive, running on Multi-Processor System-on-Chip (MPSoC) is on the rise. Timing isolation ... -
Random Modulo: A new processor cache design for real-time critical systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Comunicació de congrés
Accés obertCache memories have a huge impact on software's worst-case execution time (WCET). While enabling the seamless use of caches is key to provide the increasing levels of (guaranteed) performance required by automotive software, ... -
Randomization for safer, more reliable and secure, high-performance automotive processors
(Institute of Electrical and Electronics Engineers (IEEE), 2019-12)
Article
Accés obertThe automotive domain is witnessing a relentless transition to autonomous cars demanding high-performance processors to timely execute complex, critical, decision-making software. The other side of the coin is that ... -
Resilient random modulo cache memories for probabilistically-analyzable real-time systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertFault tolerance has often been assessed separately in safety-related real-time systems, which may lead to inefficient solutions. Recently, Measurement-Based Probabilistic Timing Analysis (MBPTA) has been proposed to estimate ... -
RPR: a random replacement policy with limited pathological replacements
(Association for Computing Machinery (ACM), 2018)
Text en actes de congrés
Accés restringit per política de l'editorialMeasurement-Based Probabilistic Timing Analysis (MBPTA) has consolidated as a technique to estimate probabilistic Worst-Case Execution Times (WCET) for critical software running on processors with high-performance hardware ... -
RunPar: An allocation algorithm for automotive applications exploiting runnable parallelism in multicores
(Association for Computing Machinery (ACM), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialAutomotive applications increasingly rely on AUTOSAR for their design and execution. AUTOSAR applications comprise functions, called runnables, that are grouped into AUTOSAR tasks. Tasks are the unit of scheduling (UoS) ... -
RVC: A mechanism for time-analyzable real-time processors with faulty caches
(2011)
Text en actes de congrés
Accés restringit per política de l'editorialGeometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM arrays such as caches. Faulty bits can be tolerated from the average performance perspective, but make critical realtime ... -
SafeLS: An open source implementation of a lockstep NOEL-V RISC-V core
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertMicrocontrollers running safety-critical applications with high integrity requirements must provide appropriate safety measures to manage random hardware faults. For instance, automotive safety regulations (e.g., ISO26262) ... -
Safety-related challenges and opportunities for GPUs in the automotive domain
(IEEE, 2018-10-09)
Article
Accés obertGPUs have been shown to cover the computing performance needs of autonomous driving (AD) systems. However, since the GPUs used for AD build on designs for the mainstream market, they may lack fundamental properties for ... -
SAFEXPLAIN: Safe and Explainable Critical Embedded Systems Based on AI
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Comunicació de congrés
Accés obertDeep Learning (DL) techniques are at the heart of most future advanced software functions in Critical Autonomous AI-based Systems (CAIS), where they also represent a major competitive factor. Hence, the economic success ... -
Seeking time-composable partitions of tasks for COTS multicore processors
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Comunicació de congrés
Accés obertThe timing verification of real-time single core systems involves a timing analysis step that yields an Execution Time Bound (ETB) for each task, followed by a schedulability analysis step, where the scheduling attributes ... -
Selección del tamaño del banco de registros y de la política de asignación de recursos en procesadores SMT
(Thomson Editores Spain, 2007)
Text en actes de congrés
Accés obertEste trabajo estudia el impacto del tamaño del banco de registros físico (BRF) en el rendimiento de procesadores Simultaneous Multithreading (SMT). Como es bien conocido, el BRF es un componente crítico en este tipo de ...
