Exploració per autor "Cazorla Almeida, Francisco Javier"
Ara es mostren els items 60-79 de 145
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LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache
(IEEE, 2019-05-16)
Comunicació de congrés
Accés obertAs implementation technology shrinks, the presence of errors in cache memories is becoming an increasing issue in all computing domains. Critical systems, e.g. space and automotive, are specially exposed and susceptible ... -
Leveraging hardware QoS to control contention in the Xilinx Zynq UltraScale+ MPSoC
(Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2021)
Text en actes de congrés
Accés obertThe interference co-running tasks generate on each other’s timing behavior continues to be one of the main challenges to be addressed before Multi-Processor System-on-Chip (MPSoCs) are fully embraced in critical systems ... -
Locality-aware cache random replacement policies
(2019-02-01)
Article
Accés obertMeasurement-Based Probabilistic Timing Analysis (MBPTA) facilitates the analysis of complex software running on hardware comprising high-performance features. MBPTA also aims at preventing additional analysis costs for ... -
Locality-aware cache random replacement policies
(Elsevier, 2019-02)
Article
Accés obertMeasurement-Based Probabilistic Timing Analysis (MBPTA) facilitates the analysis of complex software running on hardware comprising high-performance features. MBPTA also aims at preventing additional analysis costs for ... -
Main sources of variability and non-determinism in AD software: taxonomy and prospects to handle them
(Springer Nature, 2023-09)
Article
Accés restringit per política de l'editorialSafety standards in domains like automotive and avionics seek for deterministic execution (lack of jittery behavior) as a stepping stone to build a certification argument on the correct timing behavior of the system. ... -
Maximizing multithreaded multicore architectures through thread migrations
(2009)
Report de recerca
Accés obertHeterogeneity in general-purpose workloads often end up in non optimal per-thread hardware resource usage. The current trend towards multicore architectures, containing several multithreaded cores, increases the need of a ... -
Measurement-based cache representativeness on multipath programs
(Association for Computing Machinery (ACM), 2018-06)
Comunicació de congrés
Accés obertAutonomous vehicles in embedded real-time systems increase critical-software size and complexity whose performance needs are covered with high-performance hardware features like caches, which however hampers obtaining WCET ... -
Measurement-based probabilistic timing analysis for multi-path programs
(2012)
Text en actes de congrés
Accés restringit per política de l'editorialThe rigorous application of static timing analysis requires a large and costly amount of detail knowledge on the hardware and software components of the system. Probabilistic Timing Analysis has potential for reducing the ... -
Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialProbabilistic Timing Analysis (PTA) in general and its measurement-based variant called MBPTA in particular can mitigate some of the problems that impair current worst-case execution time (WCET) analysis techniques. MBPTA ... -
Measurement-based timing analysis of the AURIX caches
(Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2016)
Text en actes de congrés
Accés obertCache memories are one of the hardware resources with higher potential to reduce worst-case execution time (WCET) costs for software programs with tight real-time constraints. Yet, the complexity of cache analysis has ... -
Measuring operating system overhead on CMT processors
(IEEE Computer Society Publications, 2008)
Text en actes de congrés
Accés obertNumerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing ... -
Measuring operating system overhead on Sun UltraSparc T1 processor
(2009-06)
Text en actes de congrés
Accés obertNumerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing, ... -
MFLUSH: handling long-latency loads in SMT on-chip multiprocessors
(IEEE Computer Society Publications, 2008)
Text en actes de congrés
Accés obertNowadays, there is a clear trend in industry towards employing the growing amount of transistors on chip in replicating execution cores (CMP), where each core is Simultaneous Multithreading (SMT). State-of-the-art ... -
MLP-aware dynamic cache partitioning
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Comunicació de congrés
Accés obertThe limitation imposed by instruction-level parallelism (ILP) has motivated the use of thread-level parallelism (TLP) as a common strategy for improving processor performance. TLP paradigms such as simultaneous multithreading ... -
Modeling contention interference in crossbar-based systems via Sequence-Aware Pairing (SeAP)
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertThe Infineon AURIX TriCore family of microcontrollers has consolidated as the reference multicore computing platform for safety-critical systems in the automotive domain. As a distinctive trait, AURIX microcontrollers are ... -
Modeling high-performance wormhole NoCs for critical real-time embedded systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertManycore chips are a promising computing platform to cope with the increasing performance needs of critical real-time embedded systems (CRTES). However, manycores adoption by CRTES industry requires understanding task's ... -
Modeling the impact of process variations in worst-case energy consumption estimation
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertThe advent of autonomous power-limited systems poses a new challenge for system verification. Powerful processors needed to enable autonomous operation, are typically power-hungry, jeopardizing battery duration. Therefore, ... -
Modelling and predicting extreme behavior in critical real-time systems with advanced statistics
(Barcelona Supercomputing Center, 2020-05)
Text en actes de congrés
Accés obertIn the last decade, the market for Critical Real-Time Embedded Systems (CRTES) has increased significantly. According to Global Markets Insight [1], the embedded systems market will reach a total size of US $258 billion ... -
Modelling probabilistic cache representativeness in the presence of arbitrary access patterns
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertMeasurement-Based Probabilistic Timing Analysis (MBPTA) is a promising powerful industry-friendly method to derive worst-case execution time (WCET) estimates as needed for critical real-time embedded systems. MBPTA performs ... -
Modelling the confidence of timing analysis for time randomised caches
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertTiming is a key non-functional property in embedded real-Time systems (ERTS). ERTS increasingly require higher levels of performance that can only be sensibly provided by deploying high-performance hardware, which however ...
