Exploració per autor "Cazorla Almeida, Francisco Javier"
Ara es mostren els items 49-68 de 145
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HRM: merging hardware event monitors for improved timing analysis of complex MPSoCs
(2020-11)
Article
Accés obertThe Performance Monitoring Unit (PMU) in MPSoCs is at the heart of the latest measurement-based timing analysis techniques in Critical Embedded Systems. In particular, hardware event monitors (HEMs) in the PMU are used as ... -
HWP: hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems
(Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2018)
Text en actes de congrés
Accés obertHigh-performance processors have deployed multilevel cache (MLC) systems for decades. In the embedded real-time market, the use of MLC is also on the rise, with processors for future systems in space, railway, avionics and ... -
Implicit vs. explicit resource allocation in SMT processors
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertIn a simultaneous multithreaded (SMT) architecture, the front end of a superscalar is adapted in order to be able to fetch from several threads while the back end is shared among the threads. In this paper, we describe ... -
Improving early design stage timing modeling in multicore based real-time systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertThis paper presents a modelling approach for the timing behavior of real-time embedded systems (RTES) in early design phases. The model focuses on multicore processors - accepted as the next computing platform for RTES - ... -
Improving performance guarantees in wormhole mesh NoC designs
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertWormhole-based mesh Networks-on-Chip (wNoC) are deployed in high-performance many-core processors due to their physical scalability and low-cost. Delivering tight and time composable Worst-Case Execution Time (WCET) estimates ... -
Improving time-randomized cache design
(Barcelona Supercomputing Center, 2018-04-24)
Text en actes de congrés
Accés obertEnabling timing analysis for caches has been pursued by the critical real-time embedded systems (CRTES) community for years due to their potential to reduce worstcase execution times (WCET). Measurement-based protabilistic ... -
Improving Timing-Related Guarantees for Main Memory in Multicore Critical Embedded Systems
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Comunicació de congrés
Accés obertMain memory is one of the most complex resources to analyze in multicore-based embedded real-time systems, with contention in the memory controller and the timing constraints of the main memory device as the main contributors ... -
Increasing multicore system efficiency through intelligent bandwidth shifting
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés restringit per política de l'editorialMemory bandwidth is a crucial resource in computing systems. Current CMP/SMT processors have a significant number of cores and they can run many threads concurrently. This large thread count adds high pressure to the memory ... -
IntPred: flexible, fast, and accurate object detection for autonomous driving systems
(Association for Computing Machinery (ACM), 2020)
Text en actes de congrés
Accés obertDeep Neural-Network (DNN) based Object Detection is one of the most important and time-consuming stages of Autonomous Driving software in cars. In non-critical domains, the performance and energy requirements of object ... -
ITCA: Inter-Task Conflict-Aware CPU accounting for CMP
(2010)
Text en actes de congrés
Accés obertChip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ... -
ITCA: inter-task conflict-aware CPU accounting for CMPs
(IEEE Computer Society Publications, 2009)
Text en actes de congrés
Accés restringit per política de l'editorial -
LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache
(IEEE, 2019-05-16)
Comunicació de congrés
Accés obertAs implementation technology shrinks, the presence of errors in cache memories is becoming an increasing issue in all computing domains. Critical systems, e.g. space and automotive, are specially exposed and susceptible ... -
Leveraging hardware QoS to control contention in the Xilinx Zynq UltraScale+ MPSoC
(Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2021)
Text en actes de congrés
Accés obertThe interference co-running tasks generate on each other’s timing behavior continues to be one of the main challenges to be addressed before Multi-Processor System-on-Chip (MPSoCs) are fully embraced in critical systems ... -
Locality-aware cache random replacement policies
(2019-02-01)
Article
Accés obertMeasurement-Based Probabilistic Timing Analysis (MBPTA) facilitates the analysis of complex software running on hardware comprising high-performance features. MBPTA also aims at preventing additional analysis costs for ... -
Locality-aware cache random replacement policies
(Elsevier, 2019-02)
Article
Accés obertMeasurement-Based Probabilistic Timing Analysis (MBPTA) facilitates the analysis of complex software running on hardware comprising high-performance features. MBPTA also aims at preventing additional analysis costs for ... -
Main sources of variability and non-determinism in AD software: taxonomy and prospects to handle them
(Springer Nature, 2023-09)
Article
Accés restringit per política de l'editorialSafety standards in domains like automotive and avionics seek for deterministic execution (lack of jittery behavior) as a stepping stone to build a certification argument on the correct timing behavior of the system. ... -
Maximizing multithreaded multicore architectures through thread migrations
(2009)
Report de recerca
Accés obertHeterogeneity in general-purpose workloads often end up in non optimal per-thread hardware resource usage. The current trend towards multicore architectures, containing several multithreaded cores, increases the need of a ... -
Measurement-based cache representativeness on multipath programs
(Association for Computing Machinery (ACM), 2018-06)
Comunicació de congrés
Accés obertAutonomous vehicles in embedded real-time systems increase critical-software size and complexity whose performance needs are covered with high-performance hardware features like caches, which however hampers obtaining WCET ... -
Measurement-based probabilistic timing analysis for multi-path programs
(2012)
Text en actes de congrés
Accés restringit per política de l'editorialThe rigorous application of static timing analysis requires a large and costly amount of detail knowledge on the hardware and software components of the system. Probabilistic Timing Analysis has potential for reducing the ... -
Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialProbabilistic Timing Analysis (PTA) in general and its measurement-based variant called MBPTA in particular can mitigate some of the problems that impair current worst-case execution time (WCET) analysis techniques. MBPTA ...
