Ara es mostren els items 36-55 de 144

    • Empirical evidence for MPSoCs in critical systems: The case of NXP’s T2080 cache coherence 

      Pujol Torramorell, Roger; Tabani, Hamid; Abella Ferrer, Jaume; Hassan, Mohamed; Cazorla Almeida, Francisco Javier (IEEE, 2021)
      Comunicació de congrés
      Accés obert
      The adoption of complex MPSoCs in critical real-time embedded systems mandates a detailed analysis their architecture to facilitate certification. This analysis is hindered by the lack of a thorough understanding of the ...
    • En-route: on enabling resource usage testing for autonomous driving frameworks 

      Alcon, Miguel; Tabani, Hamid; Abella Ferrer, Jaume; Kosmidis, Leonidas; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2020-03)
      Text en actes de congrés
      Accés obert
      Software resource usage testing, including execution time bounds and memory, is a mandatory validation step during the integration of safety-related real-time systems. However, the inherent complexity of Autonomous Driving ...
    • Enabling SMT for real-time embedded systems 

      Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernandez Prieto, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
      Text en actes de congrés
      Accés obert
      In order to deal with real time constraints, current embedded processors are usually simple in-order processors with no speculation capabilities to ensure that execution times of applications are predictable. However, ...
    • Enabling unit testing of already-integrated AI software systems: The case of Apollo for autonomous driving 

      Alcón Doganoc, Miguel; Tabani, Hamid; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2021)
      Text en actes de congrés
      Accés obert
      The advanced AI-based software used for autonomous driving comprises multiple highly-coupled modules that are data and control dependent. Deploying those already-integrated software frameworks makes unit testing, a fundamental ...
    • EOmesh: combined flow balancing and deterministic routing for reduced WCET estimates in embedded real-time systems 

      Cardona Nadal, Jordi; Abella Ferrer, Jaume; Hernández Luz, Carles; Cazorla Almeida, Francisco Javier (2018-07-17)
      Article
      Accés obert
      The increasing performance needs in critical real-time embedded systems (CRTES) can only be satisfied with the use of high-performance manycore processors. While NoC-based manycore systems are popular in the high-performance ...
    • Evolutionary system for prediction and optimization of hardware architecture performance 

      Castillo, Pedro Angel; Merelo, Juan Julián; Moretó Planas, Miquel; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo; Mora, Antonio; Laredo, Juan Luís; McKee, Sally (2008-06)
      Text en actes de congrés
      Accés obert
      The design of computer architectures is a very complex problem. The multiple parameters make the number of possible combinations extremely high. Many researchers have used simulation, although it is a slow solution since ...
    • Experimental analysis on the NXP’s T2080 cache coherence: a step towards MPSoCs in critical systems 

      Pujol, Roger; Hassan, Mohamed; Cazorla Almeida, Francisco Javier (Barcelona Supercomputing Center, 2022-05)
      Text en actes de congrés
      Accés obert
      The adoption of complex MPSoCs in critical real-time embedded systems [1], [2] mandates a detailed analysis of their architecture to facilitate certification [3]. This analysis is hindered by the lack of a thorough ...
    • Fitting processor architectures for measurement-based probabilistic timing analysis 

      Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Vardanega, Tullio; Hernández, Carles; Gianarro, Andrea; Broster, Ian; Cazorla Almeida, Francisco Javier (2016-11-01)
      Article
      Accés obert
      The pressing market demand for competitive performance/cost ratios compels Critical Real-Time Embedded Systems industry to employ feature-rich hardware. The ensuing rise in hardware complexity however makes worst-case ...
    • GMAI: Understanding and exploiting the internals of GPU resource allocation in critical systems 

      Calderón Torres, Alejandro Josué; Kosmidis, Leonidas; Nicolás Ramírez, Carlos Fernando; Cazorla Almeida, Francisco Javier; Onaindia, Peio (2020-09)
      Article
      Accés obert
      Critical real-time systems require strict resource provisioning in terms of memory and timing. The constant need for higher performance in these systems has led industry to recently include GPUs. However, GPU software ...
    • GPU devices for safety-critical systems: a survey 

      Pérez Cerrolaza, Jon; Abella Ferrer, Jaume; Kosmidis, Leonidas; Calderón Torres, Alejandro Josué; Cazorla Almeida, Francisco Javier; Flores Barroso, José Luis (Association for Computing Machinery (ACM), 2023-07)
      Article
      Accés obert
      Graphics Processing Unit (GPU) devices and their associated software programming languages and frameworks can deliver the computing performance required to facilitate the development of next-generation high-performance ...
    • GPU4S: Embedded GPUs in Space 

      Kosmidis, Leonidas; Lachaize, Jérôme; Abella Ferrer, Jaume; Notebaert, Olivier; Cazorla Almeida, Francisco Javier; Steenari, David (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Text en actes de congrés
      Accés obert
      Following the same trend of automotive and avionics, the space domain is witnessing an increase in the on-board computing performance demands. This raise in performance needs comes from both control and payload parts of ...
    • GPU4S: Embedded GPUs in Space - Latest project updates 

      Kosmidis, Leonidas; Rodríguez Ferrandez, Iván; Jover Álvarez, Álvaro; Alcaide Portet, Sergi; Lachaize, Jérôme; Abella Ferrer, Jaume; Notebaert, Olivier; Cazorla Almeida, Francisco Javier; Steenari, David (2020-09)
      Article
      Accés obert
      Following the trend of other safety-critical industries like automotive and avionics, the space domain is witnessing an increase in the on-board computing performance demands. This raise in performance needs comes from ...
    • HRM: merging hardware event monitors for improved timing analysis of complex MPSoCs 

      Vilardell Moreno, Sergi; Serra Mochales, Isabel; Santalla, Roberto; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (2020-11)
      Article
      Accés obert
      The Performance Monitoring Unit (PMU) in MPSoCs is at the heart of the latest measurement-based timing analysis techniques in Critical Embedded Systems. In particular, hardware event monitors (HEMs) in the PMU are used as ...
    • HWP: hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems 

      Benedicte Illescas, Pedro; Hernandez, C.; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2018)
      Text en actes de congrés
      Accés obert
      High-performance processors have deployed multilevel cache (MLC) systems for decades. In the embedded real-time market, the use of MLC is also on the rise, with processors for future systems in space, railway, avionics and ...
    • Implicit vs. explicit resource allocation in SMT processors 

      Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernandez Garcia, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
      Text en actes de congrés
      Accés obert
      In a simultaneous multithreaded (SMT) architecture, the front end of a superscalar is adapted in order to be able to fetch from several threads while the back end is shared among the threads. In this paper, we describe ...
    • Improving early design stage timing modeling in multicore based real-time systems 

      Trilla, David; Jalle Ibarra, Javier; Fernández, Mikel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Text en actes de congrés
      Accés obert
      This paper presents a modelling approach for the timing behavior of real-time embedded systems (RTES) in early design phases. The model focuses on multicore processors - accepted as the next computing platform for RTES - ...
    • Improving performance guarantees in wormhole mesh NoC designs 

      Panic, Milos; Hernández, Carles; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Text en actes de congrés
      Accés obert
      Wormhole-based mesh Networks-on-Chip (wNoC) are deployed in high-performance many-core processors due to their physical scalability and low-cost. Delivering tight and time composable Worst-Case Execution Time (WCET) estimates ...
    • Improving time-randomized cache design 

      Benedicte Illescas, Pedro; Hernández Gañán, Carlos; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Barcelona Supercomputing Center, 2018-04-24)
      Text en actes de congrés
      Accés obert
      Enabling timing analysis for caches has been pursued by the critical real-time embedded systems (CRTES) community for years due to their potential to reduce worstcase execution times (WCET). Measurement-based protabilistic ...
    • Improving Timing-Related Guarantees for Main Memory in Multicore Critical Embedded Systems 

      Fernández de Lecea, Asier; Hassan, Mohamed; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2023)
      Comunicació de congrés
      Accés obert
      Main memory is one of the most complex resources to analyze in multicore-based embedded real-time systems, with contention in the memory controller and the timing constraints of the main memory device as the main contributors ...
    • Increasing multicore system efficiency through intelligent bandwidth shifting 

      Jiménez, Víctor; Buyuktosunoglu, Alper; Bose, Pradip; O'Connell, Francis P.; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2015)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Memory bandwidth is a crucial resource in computing systems. Current CMP/SMT processors have a significant number of cores and they can run many threads concurrently. This large thread count adds high pressure to the memory ...