Exploració per autor "Cazorla Almeida, Francisco Javier"
Ara es mostren els items 26-45 de 145
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Data bus slicing for contention-free multicore real-time memory systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertMemory access contention is one of the main contributors to tasks' execution time variability in real-Time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well ... -
Dcache Warn: an I-fetch policy to increase SMT efficiency
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertSimultaneous multithreading (SMT) processors increase performance by executing instructions from multiple threads simultaneously. These threads share the processor's resources, but also compete for them. In this environment, ... -
Deconstructing bus access control policies for real-time multicores
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialMulticores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key ... -
Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems
(Institute of Electrical and Electronics Engineers (IEEE), 2021-12)
Text en actes de congrés
Accés obertThe number of functionalities controlled by software on every critical real-time product is on the rise in domains like automotive, avionics and space. To implement these advanced functionalities, software applications ... -
Design and integration of hierarchical-placement multi-level caches for real-Time systems
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés restringit per política de l'editorialEnabling timing analysis in the presence of caches has been pursued by the real-Time embedded systems (RTES) community for years due to cache's huge potential to reduce software's worst-case execution time (WCET). However, ... -
DReAM: An approach to estimate per-Task DRAM energy in multicore systems
(2016-12)
Article
Accés obertAccurate per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is ... -
DReAM: Per-task DRAM energy metering in multicore systems
(Springer, 2014)
Text en actes de congrés
Accés obertInteraction across applications in DRAM memory impacts its energy consumption. This paper makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations, ... -
DTM: degraded test mode for fault-aware probabilistic timing analysis
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialExisting timing analysis techniques to derive Worst-Case Execution Time (WCET) estimates assume that hardware in the target platform (e.g., the CPU) is fault-free. Given the performance requirements increase in current ... -
Dynamic and execution views to improve validation, testing, and optimization of autonomous driving software
(Springer Nature, 2023-06)
Article
Accés obertThe adoption of autonomous driving (AD) software executed on high-performance multi-processor systems on chip (MPSoCs) contributes to increasing the overall system’s safety and efficiency. However, existing AD software ... -
Dynamically controlled resource allocation in SMT processors
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertSMT processors increase performance by executing instructions from several threads simultaneously. These threads use the resources of the processor better by sharing them but, at the same time, threads are competing for ... -
Empirical evidence for MPSoCs in critical systems: The case of NXP’s T2080 cache coherence
(IEEE, 2021)
Comunicació de congrés
Accés obertThe adoption of complex MPSoCs in critical real-time embedded systems mandates a detailed analysis their architecture to facilitate certification. This analysis is hindered by the lack of a thorough understanding of the ... -
En-route: on enabling resource usage testing for autonomous driving frameworks
(Association for Computing Machinery (ACM), 2020-03)
Text en actes de congrés
Accés obertSoftware resource usage testing, including execution time bounds and memory, is a mandatory validation step during the integration of safety-related real-time systems. However, the inherent complexity of Autonomous Driving ... -
Enabling SMT for real-time embedded systems
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertIn order to deal with real time constraints, current embedded processors are usually simple in-order processors with no speculation capabilities to ensure that execution times of applications are predictable. However, ... -
Enabling unit testing of already-integrated AI software systems: The case of Apollo for autonomous driving
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés obertThe advanced AI-based software used for autonomous driving comprises multiple highly-coupled modules that are data and control dependent. Deploying those already-integrated software frameworks makes unit testing, a fundamental ... -
EOmesh: combined flow balancing and deterministic routing for reduced WCET estimates in embedded real-time systems
(2018-07-17)
Article
Accés obertThe increasing performance needs in critical real-time embedded systems (CRTES) can only be satisfied with the use of high-performance manycore processors. While NoC-based manycore systems are popular in the high-performance ... -
Evaluating the computational capabilities of embedded multicore and GPU platforms for on-board image processing
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertOn-board Image Processing is one of the most computationally intensive tasks performed in space payload processing. With the constant increase in the resolution of optical sensors, new powerful architectures are needed for ... -
Evolutionary system for prediction and optimization of hardware architecture performance
(2008-06)
Text en actes de congrés
Accés obertThe design of computer architectures is a very complex problem. The multiple parameters make the number of possible combinations extremely high. Many researchers have used simulation, although it is a slow solution since ... -
Experimental analysis on the NXP’s T2080 cache coherence: a step towards MPSoCs in critical systems
(Barcelona Supercomputing Center, 2022-05)
Text en actes de congrés
Accés obertThe adoption of complex MPSoCs in critical real-time embedded systems [1], [2] mandates a detailed analysis of their architecture to facilitate certification [3]. This analysis is hindered by the lack of a thorough ... -
Fitting processor architectures for measurement-based probabilistic timing analysis
(2016-11-01)
Article
Accés obertThe pressing market demand for competitive performance/cost ratios compels Critical Real-Time Embedded Systems industry to employ feature-rich hardware. The ensuing rise in hardware complexity however makes worst-case ... -
GMAI: Understanding and exploiting the internals of GPU resource allocation in critical systems
(2020-09)
Article
Accés obertCritical real-time systems require strict resource provisioning in terms of memory and timing. The constant need for higher performance in these systems has led industry to recently include GPUs. However, GPU software ...
