Exploració per autor "Cristal Kestelman, Adrián"
Ara es mostren els items 85-104 de 129
-
Nebelung: execution environment for transactional OpenMP
Milovanovic, M; Ferrer, Roger; Gajinov, Vladimir; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (2008-06)
Article
Accés restringit per política de l'editorialFuture generations of Chip Multiprocessors (CMP) will provide dozens or even hundreds of cores inside the chip. Writing applications that benefit from the massive computational power offered by these chips is not going to ... -
NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs
Seyedi, Azam; Karakostas, Vasileios; Cosemans, Stefan; Cristal Kestelman, Adrián; Nemirovsky, Mario; Unsal, Osman (Institute of Electrical and Electronics Engineers (IEEE), 2015-07-10)
Text en actes de congrés
Accés obertIn this paper we propose a novel Content Addressable Memory (CAM) cell, NEMsCAM, based on both Nano-electro-mechanical (NEM) switches and CMOS technologies. The memory component of the proposed CAM cell is designed with ... -
Object oriented execution model (OOM)
Markovic, Nikola; Nemirovsky, Daniel; González Blanco, Ruben; Unsal, Osman Sabri; Valero Cortés, Mateo; Cristal Kestelman, Adrián (INRIA, 2011)
Text en actes de congrés
Accés obertThis paper considers implementing the Object Oriented Programming Model directly in the hardware to serve as a base to exploit object-level parallelism, speculation and heterogeneous computing. Towards this goal, we present ... -
On the resilience of deep learning for reduced-voltage FPGAs
Givaki, Kamyar; Salami, Behzad; Hojabr, Reza; Tayaranian, S. M. Reza; Khonsari, Ahmad; Rahmati, Dara; Gorgin, Saeid; Cristal Kestelman, Adrián; Unsal, Osman Sabri (Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertDeep Neural Networks (DNNs) are inherently computation-intensive and also power-hungry. Hardware accelerators such as Field Programmable Gate Arrays (FPGAs) are a promising solution that can satisfy these requirements for ... -
On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation
Salami, Behzad; Unsal, Osman S.; Cristal Kestelman, Adrián (IEEE, 2019-02-21)
Comunicació de congrés
Accés obertMachine Learning (ML) is making a strong resurgence in tune with the massive generation of unstructured data which in turn requires massive computational resources. Due to the inherently compute and power-intensive structure ... -
On the selection of adder unit in energy efficient vector processing
Ratkovic, Ivan; Palomar Pérez, Óscar; Stanic, Milan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialVector processors are a very promising solution for mobile devices and servers due to their inherently energy-efficient way of exploiting data-level parallelism. Previous research on vector architectures predominantly ... -
Out-of-order commit processors
Cristal Kestelman, Adrián; Ortega, Daniel; Llosa Espuny, José Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertModern out-of-order processors tolerate long latency memory operations by supporting a large number of in-flight instructions. This is particularly useful in numerical applications where branch speculation is normally not ... -
PAMS: pattern aware memory system for embedded systems
Hussain, Tassadaq; Sönmez, Nehir; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo; Gursal, Shakaib A. (Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés obertIn this paper, we propose a hardware mechanism for embedded multi-core memory system called Pattern Aware Memory System (PAMS). The PAMS supports static and dynamic data structures using descriptors and specialized memory ... -
ParaDIME: Parallel distributed infrastructure for minimization of energy for data centers
Rethinagiri, Santhosh Kumar; Palomar Pérez, Óscar; Sobe, Anita; Yalcin, Gulay; Knauth, Thomas; Titos Gil, Rubén; Prieto, Pablo; Schneegaß, Malte; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Felber, Pascal; Fetzer, Christof; Milojevic, Dragomir (2015-11-01)
Article
Accés obertDramatic environmental and economic impact of the ever increasing power and energy consumption of modern computing devices in data centers is now a critical challenge. On the one hand, designers use technology scaling as ... -
Physical vs. physically-aware estimation flow: case study of design space exploration of adders
Ratkovic, Ivan; Palomar Pérez, Óscar; Stanic, Milan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialSelecting an appropriate estimation method for a given technology and design is of crucial interest as the estimations guide future project and design decisions. The accuracy of the estimations of area, timing, and power ... -
POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core
Stanic, Milan; Palomar, Oscar; Hayes, Timothy; Ratkovic, Ivan; Unsal, Osman; Cristal Kestelman, Adrián (ACM, 2016-09)
Comunicació de congrés
Accés obertIn the low-end mobile processor market, power, energy and area budgets are significantly lower than in other markets (e.g. servers or high-end mobile markets). It has been shown that vector processors are a highly ... -
POSTER: an integrated vector-scalar design on an in-order ARM core
Stanic, Milan; Palomar Pérez, Óscar; Hayes, Timothy; Ratkovic, Ivan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2016)
Text en actes de congrés
Accés restringit per política de l'editorialIn the low-end mobile processor market, power, energy and area budgets are significantly lower than in other markets (e.g. servers or high-end mobile markets). It has been shown that vector processors are a highly ... -
Practical experience with Nebelung: the runtime support for transactional memory and OpenMP
Milovanovic, Milos; Ferrer, Roger; Gajinov, Vladimir; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (2007-08)
Report de recerca
Accés obertTransactional Memory (TM) is a key future technology for emerging many-cores. On the other hand, OpenMP provides a vast established base for writing parallel programs, especially for scientific applications. Combining TM ... -
Programmer-directed partial redundancy for resilient HPC
Subasi, Omer; Arias Moreno, Francisco Javier; Unsal, Osman Sabri; Labarta Mancho, Jesús José; Cristal Kestelman, Adrián (Association for Computing Machinery (ACM), 2015)
Text en actes de congrés
Accés restringit per política de l'editorialIn this work we propose partial task replication and check-pointing for task-parallel HPC applications to mitigate silent data corruption (SDC) errors. As the complete replication of all application tasks can be prohibitive ... -
PVMC: Programmable Vector Memory Controller
Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés obertIn this work, we propose a Programmable Vector Memory Controller (PVMC), which boosts noncontiguous vector data accesses by integrating descriptors of memory patterns, a specialized local memory, a memory manager in hardware, ... -
QuakeTM: Parallelizing a complex serial application using transactional memory
Gajinov, Vladimir; Zyulkyarov, Ferad; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Harris, Tim; Valero Cortés, Mateo (2008-11)
Report de recerca
Accés obert'Is transactional memory useful?' is the question that cannot be answered until we provide substantial applications that can evaluate its capabilities. While existing TM applications can partially answer the above question, ... -
RETHINK big: European roadmap for hardware anc networking optimizations for big data
Alioto, Gina; Carpenter, Paul Matthew; Cristal Kestelman, Adrián; Unsal, Osman; Leich, Marcus; Avare, Christophe (Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
Comunicació de congrés
Accés obertThis paper discusses the results of the RETHINK big Project, a 2-year Collaborative Support Action funded by the European Commission in order to write the European Roadmap for Hardware and Networking optimizations for Big ... -
ROB-free architecture proposal
González, Isidro; Galluzzi, Marco; Cristal Kestelman, Adrián; Pajuelo González, Manuel Alejandro; Santana Jaria, Oliverio J.; Valero Cortés, Mateo (2007-09)
Report de recerca
Accés obertModern processors improve performance by taking advantage of the instruction level parallelism (ILP) by means of allowing hundreds of instructions in flight. However, they still have to face an important source of degradation ... -
Runtime-aware architectures
Casas, Marc; Moretó Planas, Miquel; Álvarez Martí, Lluc; Castillo Villar, Emilio; Chasapis, Dimitrios; Hayes, Timothy; Jaulmes, Luc; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Springer, 2015)
Text en actes de congrés
Accés obertIn the last few years, the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore’s Law have vanished. When uni-cores were the norm, hardware design was decoupled from the software ... -
Sargantana: an academic SoC RISC-V processor in 22nm FDSOI technology
Doblas Font, Max; Candón Arenas, Gerard; Carril Gil, Xavier; Dominguez de la Rocha, Marc; Erra, Enric; González Trejo, Alberto; Jiménez, Víctor; Kostalampros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel; López Paradís, Guillem; Mendoza Escobar, Jonnatan; Oltra Oltra, Josep Angel; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Rodas Quiroga, Narcís; Reggiani, Enrico; Rodriguez, Mario; Rojas Morales, Carlos; Ruiz Ramirez, Abraham Josafat; Safadi Figueroa, Hugo Ernesto; Soria Pardos, Víctor; Vargas Valdivieso, Iván; Arreza, Fernando; Figueras Bagué, Roger; Fontova Muste, Pau; Marimon Illana, Joan; Aragonès Cervera, Xavier; Cristal Kestelman, Adrián; Mateo Peña, Diego; Moll Echeto, Francisco de Borja; Moretó Planas, Miquel; Palomar Pérez, Óscar; Sonmez, Nehir; Unsal, Osman Sabri; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2023)
Comunicació de congrés
Accés obertThis paper describes the Sargantana System on chip (SoC), a 64-bit RISC-V single core processor designed by a number of academic institutions and manufactured in 22 nm FDSOI technology: BSC, UPC, UB, UAB, CIC-IPN and IMB-CNM ...