Exploració per autor "Cristal Kestelman, Adrián"
Ara es mostren els items 29-48 de 129
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Circuit design of a dual-versioning L1 data cache for optimistic concurrency
(2011)
Report de recerca
Accés obertThis paper proposes a novel L1 data cache design with dual-versioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this new cache architecture, each dvSRAM cell ... -
Circuit design of a novel adaptable and reliable L1 data cache
(2013)
Text en actes de congrés
Accés obertThis paper proposes a novel adaptable and reliable L1 data cache design (Adapcache) with the unique capability of automatically adapting itself for different supply voltage levels and providing the highest reliability. ... -
Clock gate on abort: Towards energy-efficient hardware transactional memory
(Institute of Electrical and Electronics Engineers (IEEE), 2009)
Text en actes de congrés
Accés obertTransactional Memory (TM) is an emerging technology which promises to make parallel programming easier compared to earlier lock based approaches. However, as with any form of speculation, Transactional Memory too wastes a ... -
Commit on overflow
(2014)
Report de recerca
Accés obertCurrent commercial CPUs have hardware support for speculative lock elision (SLE). SLE tries to elide the lock by speculatively executing lock protected critical section. If the speculation fails, SLE acquires the lock and ... -
Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories
(IEEE, 2018-12-13)
Comunicació de congrés
Accés obertIn this work, we evaluate aggressive undervolting, i.e., voltage scaling below the nominal level to reduce the energy consumption of Field Programmable Gate Arrays (FPGAs). Usually, voltage guardbands are added by chip ... -
CRC-based memory reliability for task-parallel HPC applications
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés restringit per política de l'editorialMemory reliability will be one of the major concerns for future HPC and Exascale systems. This concern is mostly attributed to the expected massive increase in memory capacity and the number of memory devices in Exascale ... -
DaSH: a benchmark suite for hybrid dataflow and shared memory programming models
(2015-06-01)
Article
Accés restringit per política de l'editorialThe current trend in development of parallel programming models is to combine different well established models into a single programming, model in order to support efficient implementation of a wide range of real world ... -
DaSH: a benchmark suite for hybrid dataflow and shared memory programming models: with comparative evaluation of three hybrid dataflow models
(Association for Computing Machinery (ACM), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialThe current trend in development of parallel programming models is to combine different well established models into a single programming model in order to support efficient implementation of a wide range of real world ... -
Determinism at standard-library level in TM-based applications
(2017-02-01)
Article
Accés obertDeterministic execution of a multi-threaded application guarantees that threads access shared memory in the same order and the application gives the same output whenever it runs with the same input parameters. Determinism ... -
DeTrans: Deterministic and parallel execution of transactions
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialDeterministic execution of a multithreaded application guarantees the same output as long as the application runs with the same input parameters. Determinism helps a programmer to test and debug an application and to provide ... -
Direct instruction wakeup for out-of-order processors
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertInstruction queues consume a significant amount of power in high-performance processors, primarily due to instruction wakeup logic access to the queue structures. The wakeup logic delay is also a critical timing parameter. ... -
DLP acceleration on general purpose cores
(Barcelona Supercomputing Center, 2015-05-05)
Text en actes de congrés
Accés obertHigh-performance and power-efficient multimedia computing drives the design of modern and increasingly utilized mobile devices. State-of-the-art low power processors already utilize chip multiprocessors (CMP) that add ... -
DVINO: A RISC-V vector processor implemented in 65nm technology
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Comunicació de congrés
Accés obertThis paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM ... -
Dynamic transaction coalescing
(Association for Computing Machinery (ACM), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialPrior work in Software Transactional Memory has identified high overheads related to starting and committing transactions that may degrade the application performance. To amortize these overheads, transaction coalescing ... -
Dynamic-vector execution on a general purpose EDGE chip multiprocessor
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialThis paper proposes a cost-effective technique that morphs the available cores of a low power chip multiprocessor (CMP) into an accelerator for data parallel (DLP) workloads. Instead of adding a special-purpose vector ... -
EcoTM: Conflict-aware economical unbounded hardware transactional memory
(Elsevier, 2013)
Text en actes de congrés
Accés obertTransactional Memory (TM) is a promising paradigm for parallel programming. TM allows a thread to make a series of memory accesses as a single, atomic, transaction, while avoiding deadlocks, livelocks, and other problems ... -
EMVS: Embedded Multi Vector-core System
(2018-06)
Article
Accés obertWith the increase in the density and performance of digital electronics, the demand for a power-efficient high-performance computing (HPC) system has been increased for embedded applications. The existing embedded HPC ... -
Evaluating built-in ECC of FPGA on-chip memories for the mitigation of undervolting faults
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertVoltage underscaling below the nominal level is an effective solution for improving energy efficiency in digital circuits, e.g., Field Programmable Gate Arrays (FPGAs). However, further undervolting below a safe voltage ... -
Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés obertGraph500 is a data intensive application for high performance computing and it is an increasingly important workload because graphs are a core part of most analytic applications. So far there is no work that examines if ... -
EVX: vector execution on low power EDGE cores
(European Interactive Digital Advertising Alliance (EDAA), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialIn this paper, we present a vector execution model that provides the advantages of vector processors on low power, general purpose cores, with limited additional hardware. While accelerating data-level parallel (DLP) ...
