Exploració per autor "Jiménez González, Daniel"
Ara es mostren els items 11-30 de 47
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Chained in-order/out-of-order doublecore architecture
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertComplexity is one of the most important problems facing microarchitects. It is exacerbated by the application of optimizations, by scaling to higher issue widths and, in general, by increasing the size of microprocessor ... -
Characterizing and improving the performance of many-core task-based parallel programming runtimes
(2017)
Text en actes de congrés
Accés restringit per política de l'editorialParallel task-based programming models like OpenMP support the declaration of task data dependences. This information is used to delay the task execution until the task data is available. The dependences between tasks are ... -
Design and implementation of an architecture-aware hardware runtime for heterogeneous systems
(Barcelona Supercomputing Center, 2020-05)
Text en actes de congrés
Accés obertParallel computing has become the norm to gain performance in multicore and heterogeneous systems. Many programming models allow to exploit this parallelism with easy to use tools. In this work we focus on task-based ... -
Enabling HW-based task scheduling in large multicore architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2024-01)
Article
Accés obertDynamic Task Scheduling is an enticing programming model aiming to ease the development of parallel programs with intrinsically irregular or data-dependent parallelism. The performance of such solutions relies on the ability ... -
Exploiting parallelism on GPUs and FPGAs with OmpSs
(Association for Computing Machinery (ACM), 2017)
Text en actes de congrés
Accés obertThis paper presents the OmpSs approach to deal with heterogeneous programming on GPU and FPGA accelerators. The OmpSs programming model is based on the Mercurium compiler and the Nanos++ runtime. Applications are annotated ... -
Extending OpenMP to survive the heterogeneous multi-core era
(2010-10)
Article
Accés restringit per política de l'editorial -
Fast evaluation methodology for automatic custom hardware prototyping
(2009-06)
Text en actes de congrés
Accés obertHardware customization for scientific applications has shown a big potential for reducing power consumption and increasing performance. In particular, the automatic generation of ISA extensions for General-Purpose Processors ... -
FPGA framework improvements for HPC applications
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertIn modern FPGA devices, place and route has become an increasingly difficult task due to an increase in resources and device complexity. This results in an exponential increase of implementation possibilities. Such a huge ... -
Heterogeneous tasking on SMP/FPGA SoCs: The case of OmpSs and the Zynq
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialOmpSs is a directive-based programming model that uses OpenMP-like directives, that allow to execute the tasks annotated on both the SMPs and as FPGA kernels on modern SoC processors, like the Xilinx Zynq platform. OmpSs ... -
Implementation of the K-Means Algorithm on Heterogeneous Devices: A Use Case Based on an Industrial Dataset
(IOS Press, 2018)
Comunicació de congrés
Accés obertThis paper presents and analyzes a heterogeneous implementation of an industrial use case based on K-means that targets symmetric multiprocessing (SMP), GPUs and FPGAs. We present how the application can be optimized from ... -
Improving performance of HPC kernels on FPGAs using high-level resource management
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Comunicació de congrés
Accés obertIn state-of-the-art FPGA, especially in chiplet-based devices, place and route has become an important challenge due to an increase in device size and complexity. In the same way, off-chip memory resources have grown in ... -
Improving resource usage in large FPGA accelerators
(Barcelona Supercomputing Center, 2022-05)
Text en actes de congrés
Accés obertIn modern FPGA devices, place and route has become a difficult task for the underlying FPGA implementation tools. This is caused by an increase of device size and complexity. As devices grow in size and number of resources, ... -
Improving the discovery and clustering of three-dimensional protein patterns with OpenMP
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertThe discovery of conserved three-dimensional (3D) amino-acid patterns among a set of protein structures can be useful, for instance, to predict the functions of unknown proteins or for the rational design of multi-target ... -
LEGaTO: Low-energy, secure, and resilient toolset for heterogeneous computing
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertThe LEGaTO project leverages task-based programming models to provide a software ecosystem for Made in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of ... -
LightDock: a new multi-scale approach to protein-protein docking
(2018-01)
Article
Accés obertMotivation: Computational prediction of protein-protein complex structure by docking can provide structural and mechanistic insights for protein interactions of biomedical interest. However, current methods struggle with ... -
Metodología para la generación y evaluación automática de hardware específico
(2009-09)
Text en actes de congrés
Accés obertEn el área de la bioinformática podemos encontrar aplicaciones que suponen un reto para el diseño de nuevas arquitecturas de procesadores en términos de rendimiento, ya que sus características difieren de las de las ... -
MInGLE: An efficient framework for domain acceleration using low-power specialized functional units
(2016-06)
Article
Accés obertThe end of Dennard scaling leads to new research directions that try to cope with the utilization wall in modern chips, such as the design of specialized architectures. Processor customization utilizes transistors more ... -
OmpSs@cloudFPGA: An FPGA task-based programming model with message passing
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertNowadays, a new parallel paradigm for energy-efficient heterogeneous hardware infrastructures is required to achieve better performance at a reasonable cost on high-performance computing applications. Under this new paradigm, ... -
OmpSs@FPGA framework for high performance FPGA computing
(Institute of Electrical and Electronics Engineers (IEEE), 2021-12-01)
Article
Accés obertThis paper presents the new features of the OmpSs@FPGA framework. OmpSs is a data-flow programming model that supports task nesting and dependencies to target asynchronous parallelism and heterogeneity. OmpSs@FPGA is the ... -
OmpSs@Zynq All-Programmable SoC Ecosystem
(Association for Computing Machinery (ACM), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialOmpSs is an OpenMP-like directive-based programming model that includes heterogeneous execution (MIC, GPU, SMP, etc.) and runtime task dependencies management. Indeed, OmpSs has largely influenced the recently appeared ...
